JPS57152133A - Die bonding method - Google Patents

Die bonding method

Info

Publication number
JPS57152133A
JPS57152133A JP56035252A JP3525281A JPS57152133A JP S57152133 A JPS57152133 A JP S57152133A JP 56035252 A JP56035252 A JP 56035252A JP 3525281 A JP3525281 A JP 3525281A JP S57152133 A JPS57152133 A JP S57152133A
Authority
JP
Japan
Prior art keywords
dice
lead frame
line
direction forming
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56035252A
Other languages
Japanese (ja)
Inventor
Akira Komamiya
Masayuki Shimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinkawa Ltd
Original Assignee
Shinkawa Ltd
Shinkawa Seisakusho Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinkawa Ltd, Shinkawa Seisakusho Co Ltd filed Critical Shinkawa Ltd
Priority to JP56035252A priority Critical patent/JPS57152133A/en
Publication of JPS57152133A publication Critical patent/JPS57152133A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To enable to perform precisely die bonding inclining the dice at any angles freely by a method wherein a wafer having the numerous dice is incliningly put on a table, and the table is made to transfer in the X and Y directions along the direction forming a line of dice. CONSTITUTION:When the dice 15 are to be bonded to a lead frame 10 inclining at angles theta deg. in relation to the direction forming the line thereof, the wafer 23 is put on the table 20 at first as to make the direction forming the line of the dice 15 to have the inclination of theta deg. in relation to the lead frame. After then the table 20 is placed as the positions of the central point A, B of the adjoining arbitrary dice 15 to coincide with the pick up position, and the dice are sent in order into the prescribed pick up position transferring the table deciding the necessary X, Y directional transferring quantities DELTAX1, DELTAY1 to be supplied to the lead frame 11. Then the die 15 is bonded to the lead frame 11, while positioning operation of the next die 15 is performed, and the same operation is repeated thereafter.
JP56035252A 1981-03-13 1981-03-13 Die bonding method Pending JPS57152133A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56035252A JPS57152133A (en) 1981-03-13 1981-03-13 Die bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56035252A JPS57152133A (en) 1981-03-13 1981-03-13 Die bonding method

Publications (1)

Publication Number Publication Date
JPS57152133A true JPS57152133A (en) 1982-09-20

Family

ID=12436626

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56035252A Pending JPS57152133A (en) 1981-03-13 1981-03-13 Die bonding method

Country Status (1)

Country Link
JP (1) JPS57152133A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5978538A (en) * 1982-10-27 1984-05-07 Toshiba Corp Die bonder
JPS5990932A (en) * 1982-11-16 1984-05-25 Toshiba Corp Pellet mounting apparatus
WO2008095865A1 (en) * 2007-02-06 2008-08-14 Oerlikon Assembly Equipment Ag, Steinhausen Method for mounting semiconductor chips on a substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54158874A (en) * 1978-06-06 1979-12-15 Matsushita Electronics Corp Dies bonding unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54158874A (en) * 1978-06-06 1979-12-15 Matsushita Electronics Corp Dies bonding unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5978538A (en) * 1982-10-27 1984-05-07 Toshiba Corp Die bonder
JPS5990932A (en) * 1982-11-16 1984-05-25 Toshiba Corp Pellet mounting apparatus
WO2008095865A1 (en) * 2007-02-06 2008-08-14 Oerlikon Assembly Equipment Ag, Steinhausen Method for mounting semiconductor chips on a substrate

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