JPS57143838A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57143838A
JPS57143838A JP56029669A JP2966981A JPS57143838A JP S57143838 A JPS57143838 A JP S57143838A JP 56029669 A JP56029669 A JP 56029669A JP 2966981 A JP2966981 A JP 2966981A JP S57143838 A JPS57143838 A JP S57143838A
Authority
JP
Japan
Prior art keywords
electrode
bump
metal
substrate
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56029669A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6221268B2 (enrdf_load_stackoverflow
Inventor
Hiroshi Shibata
Takashi Kondo
Masanobu Obara
Hidefumi Nakada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56029669A priority Critical patent/JPS57143838A/ja
Publication of JPS57143838A publication Critical patent/JPS57143838A/ja
Publication of JPS6221268B2 publication Critical patent/JPS6221268B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP56029669A 1981-02-27 1981-02-27 Manufacture of semiconductor device Granted JPS57143838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56029669A JPS57143838A (en) 1981-02-27 1981-02-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56029669A JPS57143838A (en) 1981-02-27 1981-02-27 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57143838A true JPS57143838A (en) 1982-09-06
JPS6221268B2 JPS6221268B2 (enrdf_load_stackoverflow) 1987-05-12

Family

ID=12282513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56029669A Granted JPS57143838A (en) 1981-02-27 1981-02-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57143838A (enrdf_load_stackoverflow)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6312142A (ja) * 1986-05-30 1988-01-19 エイ・ティ・アンド・ティ・コーポレーション はんだ継手の形状の制御方法
WO1994024694A1 (en) * 1993-04-14 1994-10-27 Amkor Electronics, Inc. Interconnection of integrated circuit chip and substrate
US5523697A (en) * 1993-09-03 1996-06-04 Micron Technology, Inc. Testing apparatus for engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof
US5585282A (en) * 1991-06-04 1996-12-17 Micron Technology, Inc. Process for forming a raised portion on a projecting contact for electrical testing of a semiconductor
US5795818A (en) * 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method
US5849633A (en) * 1994-03-07 1998-12-15 Micron Technology, Inc. Electrically conductive projections and semiconductor processing method of forming same
EP0764352A4 (en) * 1994-06-07 2000-03-15 Tessera Inc CONTACTS AND MICROELECTRONIC ASSEMBLIES
US6204089B1 (en) * 1999-05-14 2001-03-20 Industrial Technology Research Institute Method for forming flip chip package utilizing cone shaped bumps
US6205660B1 (en) 1994-06-07 2001-03-27 Tessera, Inc. Method of making an electronic contact
JP2002121698A (ja) * 2000-10-13 2002-04-26 Sony Corp 半導体製造装置および半導体装置の製造方法
US6482676B2 (en) * 1997-01-09 2002-11-19 Fujitsu Limited Method of mounting semiconductor chip part on substrate
JP2009246166A (ja) * 2008-03-31 2009-10-22 Fujitsu Ltd 電子部品パッケージおよび基板ユニット並びにプリント配線板およびその製造方法
US7679084B2 (en) * 2000-12-29 2010-03-16 Lg Display Co., Ltd. Thin film transistor array panel and method for fabricating the same
WO2010067610A1 (ja) * 2008-12-10 2010-06-17 三洋電機株式会社 半導体モジュール、半導体モジュールの製造方法および携帯機器

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6312142A (ja) * 1986-05-30 1988-01-19 エイ・ティ・アンド・ティ・コーポレーション はんだ継手の形状の制御方法
US5585282A (en) * 1991-06-04 1996-12-17 Micron Technology, Inc. Process for forming a raised portion on a projecting contact for electrical testing of a semiconductor
WO1994024694A1 (en) * 1993-04-14 1994-10-27 Amkor Electronics, Inc. Interconnection of integrated circuit chip and substrate
US5478007A (en) * 1993-04-14 1995-12-26 Amkor Electronics, Inc. Method for interconnection of integrated circuit chip and substrate
US7098475B2 (en) 1993-09-03 2006-08-29 Micron Technology, Inc. Apparatuses configured to engage a conductive pad
US7330036B2 (en) 1993-09-03 2008-02-12 Micron Technology, Inc. Engagement Probes
US6380754B1 (en) 1993-09-03 2002-04-30 Micron Technology, Inc. Removable electrical interconnect apparatuses including an engagement proble
US5523697A (en) * 1993-09-03 1996-06-04 Micron Technology, Inc. Testing apparatus for engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof
US7026835B2 (en) 1993-09-03 2006-04-11 Micron Technology, Inc. Engagement probe having a grouping of projecting apexes for engaging a conductive pad
US6833727B2 (en) 1993-09-03 2004-12-21 Micron Technology, Inc. Method and apparatus for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability
US6124721A (en) * 1993-09-03 2000-09-26 Micron Technology, Inc. Method of engaging electrically conductive test pads on a semiconductor substrate
US6127195A (en) * 1993-09-03 2000-10-03 Micron Technology, Inc. Methods of forming an apparatus for engaging electrically conductive pads and method of forming a removable electrical interconnect apparatus
US6686758B1 (en) 1993-09-03 2004-02-03 Micron Technology, Inc. Engagement probe and apparatuses configured to engage a conductive pad
US6657450B2 (en) 1993-09-03 2003-12-02 Micron Technology, Inc. Methods of engaging electrically conductive test pads on a semiconductor substrate removable electrical interconnect apparatuses, engagement probes and removable engagement probes
US5869787A (en) * 1994-03-07 1999-02-09 Micron Technology, Inc. Electrically conductive projections
US6093643A (en) * 1994-03-07 2000-07-25 Micron Technology, Inc. Electrically conductive projections and semiconductor processing method of forming same
US5849633A (en) * 1994-03-07 1998-12-15 Micron Technology, Inc. Electrically conductive projections and semiconductor processing method of forming same
US6255213B1 (en) 1994-03-07 2001-07-03 Micron Technology, Inc. Method of forming a structure upon a semiconductive substrate
US6441320B2 (en) 1994-03-07 2002-08-27 Micron Technology, Inc. Electrically conductive projections having conductive coverings
EP0764352A4 (en) * 1994-06-07 2000-03-15 Tessera Inc CONTACTS AND MICROELECTRONIC ASSEMBLIES
US6938338B2 (en) 1994-06-07 2005-09-06 Tessera, Inc. Method of making an electronic contact
US6205660B1 (en) 1994-06-07 2001-03-27 Tessera, Inc. Method of making an electronic contact
US6163463A (en) * 1996-12-06 2000-12-19 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection
US5795818A (en) * 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method
US6482676B2 (en) * 1997-01-09 2002-11-19 Fujitsu Limited Method of mounting semiconductor chip part on substrate
US6204089B1 (en) * 1999-05-14 2001-03-20 Industrial Technology Research Institute Method for forming flip chip package utilizing cone shaped bumps
JP2002121698A (ja) * 2000-10-13 2002-04-26 Sony Corp 半導体製造装置および半導体装置の製造方法
US7679084B2 (en) * 2000-12-29 2010-03-16 Lg Display Co., Ltd. Thin film transistor array panel and method for fabricating the same
JP2009246166A (ja) * 2008-03-31 2009-10-22 Fujitsu Ltd 電子部品パッケージおよび基板ユニット並びにプリント配線板およびその製造方法
WO2010067610A1 (ja) * 2008-12-10 2010-06-17 三洋電機株式会社 半導体モジュール、半導体モジュールの製造方法および携帯機器

Also Published As

Publication number Publication date
JPS6221268B2 (enrdf_load_stackoverflow) 1987-05-12

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