JPS57143627A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS57143627A
JPS57143627A JP3017481A JP3017481A JPS57143627A JP S57143627 A JPS57143627 A JP S57143627A JP 3017481 A JP3017481 A JP 3017481A JP 3017481 A JP3017481 A JP 3017481A JP S57143627 A JPS57143627 A JP S57143627A
Authority
JP
Japan
Prior art keywords
mpu6
bus
circuit
input
main control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3017481A
Other languages
English (en)
Inventor
Seiichi Hattori
Kunio Kanda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Fujitsu Fanuc Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp, Fujitsu Fanuc Ltd filed Critical Fanuc Corp
Priority to JP3017481A priority Critical patent/JPS57143627A/ja
Publication of JPS57143627A publication Critical patent/JPS57143627A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP3017481A 1981-03-03 1981-03-03 Data processing system Pending JPS57143627A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3017481A JPS57143627A (en) 1981-03-03 1981-03-03 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3017481A JPS57143627A (en) 1981-03-03 1981-03-03 Data processing system

Publications (1)

Publication Number Publication Date
JPS57143627A true JPS57143627A (en) 1982-09-04

Family

ID=12296381

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3017481A Pending JPS57143627A (en) 1981-03-03 1981-03-03 Data processing system

Country Status (1)

Country Link
JP (1) JPS57143627A (ja)

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