JPS57139851A - Serial-parallel converter - Google Patents

Serial-parallel converter

Info

Publication number
JPS57139851A
JPS57139851A JP2595481A JP2595481A JPS57139851A JP S57139851 A JPS57139851 A JP S57139851A JP 2595481 A JP2595481 A JP 2595481A JP 2595481 A JP2595481 A JP 2595481A JP S57139851 A JPS57139851 A JP S57139851A
Authority
JP
Japan
Prior art keywords
flop
flip
serial
clock
selective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2595481A
Other languages
Japanese (ja)
Inventor
Hidetsugu Komiya
Michiya Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Fujitsu Fanuc Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp, Fujitsu Fanuc Ltd filed Critical Fanuc Corp
Priority to JP2595481A priority Critical patent/JPS57139851A/en
Publication of JPS57139851A publication Critical patent/JPS57139851A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To execute serial-parallel conversion of optional bit length, and to econimically repair a device when it is faulty, by providing a serial-parallel converting unit element of 1 bit portion in accordance with each parallel output bit, and constituting it by cascade connection. CONSTITUTION:When a clock pulse (cp) and a selective strobe pulse (sp) are applied simultaneously to a clock signal input terminal CLIN and a selective strobe signal input terminal SBIN, a flip-flop FF1 is started by an output of an AND circuit AND1, a data on a data line lD by its timing is set to the flip-flop FF1. The clock pulse (cp) is also applied to a clock terminal C of a flip-flop FF2, the selective strobe signal is set to the flip-flop FF2, its output Q is set to ''1'', and this flip-flop FF2 delays the strobe pulse (sp) by clock period and sends it out to a serial-parallel converting unit element of the next stage.
JP2595481A 1981-02-24 1981-02-24 Serial-parallel converter Pending JPS57139851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2595481A JPS57139851A (en) 1981-02-24 1981-02-24 Serial-parallel converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2595481A JPS57139851A (en) 1981-02-24 1981-02-24 Serial-parallel converter

Publications (1)

Publication Number Publication Date
JPS57139851A true JPS57139851A (en) 1982-08-30

Family

ID=12180146

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2595481A Pending JPS57139851A (en) 1981-02-24 1981-02-24 Serial-parallel converter

Country Status (1)

Country Link
JP (1) JPS57139851A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6213126A (en) * 1985-07-11 1987-01-21 Nec Corp Data conversion circuit
EP0251151A2 (en) * 1986-07-03 1988-01-07 Integrated Device Technology, Inc. Programmable fifo buffer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4995547A (en) * 1972-10-20 1974-09-10

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4995547A (en) * 1972-10-20 1974-09-10

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6213126A (en) * 1985-07-11 1987-01-21 Nec Corp Data conversion circuit
EP0251151A2 (en) * 1986-07-03 1988-01-07 Integrated Device Technology, Inc. Programmable fifo buffer

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