SU1403378A1 - Serial-to-parallel code converter - Google Patents

Abstract

The invention relates to the field of automation and high-tech equipment. The purpose of the invention is to increase the reliability of the device. The device contains a shift register 1, trigger 2 modes, an OF element, a generator of 4 clock pulses, an RS flip-flop 5, a delay element 6, a modulator two modulo 7, information input 8, control inputs 9, information outputs 10, the control outputs 11-13. 1 il.

Description

The invention relates to automation and computing and can be used in digital channel data transmission systems to convert a serial code into a parallel code.

The purpose of the invention is to increase the reliability of the conversion.

The drawing shows the block diagram of the device.

The device contains a shift register 1, trigger 2 mode, element 3 And, the generator .4 clock pulses, RS-flip-flop 5, element 6 delay, adder 7 modulo two, information 8, control 9 inputs, information 10 and control 11- 13 exits.

The device works as follows.

The control input 9 receives a signal that writes 1 to the first digit of register 1, and to the remaining bits, O, and simultaneously sets the RS flip-flop 5 and flip-flop 2 modes to the initial state. Trigger 2 (output 1) starts the 4 clock pulse generator and opens the

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3378

The torch closes element 3, prohibiting reception of information, and the operation of the 4-clock pulse generator stops.

If in the process of receiving a sequential code malfunctions occurred in element 3 I, which causes distortion of a particular bit, which goes simultaneously to register 1 and to adder 7 modulo 2, and the second input of adder 7.c of delay element 6 receives an undistorted code value bit, then at the output of the adder 7

Appears 1, which, acting on the first input to the RS-flip-flop 5, causes the appearance of the Scrap signal at the control output of the device 13.

The device works in negative logic.

Claims (1)

Invention Formula A device for converting a serial code into a parallel one, containing a clock pulse generator, the output of which is connected to a clock input of a (n + 2) -shift shift register, where n is the code width, the outputs of which are 35 Ment 3 I. With the arrival of code JQ informational outputs of the device, the output of the (n + 1) -th bit — the first control output of the device; the output of the (n + 2) -th bit is the second control output of the device and connected to the S input of the RS flip-flop, the output of which is the third control output of the device and connected to the reset input of the mode trigger, the setup input of which is combined with the input of the shift register and the R input of the RS flip-flop, is control of the device input, the output of the mode trigger is connected to the first input of the I element, the second input of which is pulse device 8 on Exit member 3 and formed by a pulse sequence, which is recorded in the shift register 1. In the case of receiving the expected n-bits of a sequential code without a failure in register 1 operation, the (n + 1) and (n + 2) -th bits of this register will be recorded with code 10. The occurrence of this combination at outputs 11 and 12 indicates the end of the conversion of the serial code to parallel and accompanying given by the second signal The end of the code 45 information input device combining with the control bits of the register. If in the process of shifting 1, which was previously written to the register, the latter fails, then with a combination of 10 in the (n + 1) -m and (n + 2) -th bits of the register appears prematurely and 1 from the output (n +2) -th bit sets the RS-flip-flop 5 to the opposite state, as a result of which the Marriage signal is generated, pressed on the control input 13, and the trigger 2 of the modes is set to the state (at the output O), and the output of the element And it is connected to the information input of the shift register, characterized in that, with the aim of increasing the reliability of the conversion ani, the device has two modulo two and a delay element whose input is connected to the input of the element, the output is connected to the first input of the modulo two adder, the second input of which is connected to the output of the element And, the output of the modulo two is connected to the S input RS-trigger, clock generator input is connected to the output of the mode trigger.  the information input of the device, the output of the element I is connected to the information input of the shift register, characterized in that, in order to increase the reliability of the conversion, a modulo two adder and a delay element whose input is connected to the input of the element I are entered into the device; modulo two, the second input of which is connected to the output of the element I, the output of the modulo two adder is connected to the S input of the RS flip-flop, the input of the clock generator is connected to the output of the mode trigger.