SU1211733A1 - Device for generating modulo 3 remainder - Google Patents

Description

The invention relates to computing and is intended for use in universal and specialized digital computers for hardware control of the transmission of large arrays of binary numbers in parallel code and arithmetic operations on them by generating residuals of numbers modulo three.

The aim of the invention is to increase the speed of the device.

The drawing shows the fuction scheme of the device.

The device contains one-bit adders 1, combined into blocks 2j of addition, triggers 3, combined into groups A, even 5 and odd 6 informational inputs of the device, a tact input 7 of the device, and outputs 8.9 of the device. ..

The introduction of trigger groups 3 located between groups of add-on blocks 2 makes it possible to organize a conveyor method for obtaining a convolution modulo three. In this device, monitored numbers arrive at the input one by one, and with some delay at the output of the device, the modulus of convolution is formed for these numbers in the same sequence as they arrive at the input of the device. The rate of formation of the convolution values modulo three is equal to the rate of controlled numbers.

A device for forming the residue modulo three works as follows.

The information inputs 5,6 of the device receives a controlled number. The device can work with random numbers. If the size of the number is not 2, where

to 2,3 ..., then the unused inputs of the add-on blocks 2 are connected to the logical bus O (not shown J.

When the first clock pulse arrives at the clock input 7 of the device, the triggers 3 of the first group A.1 record modulo three four-digit numbers generated by two single-digit adders 1 of the 2 addition blocks of the first group.

Then, the information inputs 5.6 of the device arrive, the second controlled number, and at the output of each block 2 of the addition of the first group, a two-digit number is again generated (modulo three).

When the second clock pulse arrives at the clock input 7 of the device, triggers 3 of the second group 4.2 accumulate modulo three four-bit digits composed of the output signals of the addition group 2 of the previous group. At the same time, the triggers 3 of the first group 4.1 record modulo three four-digit residues composed of the corresponding bits of the second controlled number.

After applying m clocks to the clock input 7 of the device, the modulo three residuals of the first monitored number are formed at the outputs 8.9 of the device,

Then, for each clock signal arriving at the device clock input 7, at the outputs 8.9 of the device, residues modulo three consecutive controlled numbers are generated.

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Claims (1)

DEVICE FOR FORMING THE RESIDUAL BY MODULE THREE, containing m groups of addition blocks (2 ^rn <bS2 ^mi4 , where η is the bit of the controlled number), each of which consists of two single-bit adders, the first information inputs of the first and second single-bit adders being respectively the first and the second inputs of the addition unit, the second information inputs of the first and second single-digit adders of each addition unit are the third and fourth inputs of the addition unit, respectively, in each addition unit the outputs are wasp first and second one-bit adders are connected respectively to the inputs of the first and second transfer of one-bit adders informational outputs of the first and second one-bit adders of each block of addition are respectively first and second outputs of the addition unit adding the amount of blocks in the first To the К group K ₍ = - £ - (round up to the integer up), the number of addition blocks in each Eth group K £ = / 1 with firn / (round up to the whole up), the inputs of the addition blocks of the first group are information inputs of the device, characterized in that, in order to increase the speed of the device, hl trigger groups are introduced into it, the number of triggers in each t-th group P; = 2 K; iitn), the first and second outputs of each j-th block additions (1 έ j έ P;) of the t-th group are connected respectively to the information inputs of the (2j -1) th and 2j th triggers group, the synchronization inputs of the triggers of all groups are combined and form the device clock, the first, second, third and fourth inputs of each j-th block of addition of the C-th group are connected respectively to the outputs (4j -z) -go, ^ 4j - 2) -th, (4j-1) -th and 4j -th triggers (B - 1) -th group, the outputs of the triggers of the last group are the information outputs of the device. U ..., 1211733