SU1552395A1 - Device for shaping optimum discrete-frequency signals - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase the ensemble of generated discrete-frequency signals. The device for generating optimal discrete-frequency signals contains a block 1 of RF generators, a generator of 2 clock pulses, a shaper 3 numbers, a key 4, an adder 5 modulo (N + 1) and a decoder 6. The goal is achieved by introducing the adder 7 modulo V, decoders 8 and 12, the matrix Permanent Storage Unit 9, the multiplexer 10, the storage register 11 of the original code sequence and the number generators 13 and 14, which enable one of the V RF generators of Unit 1 for the time determined by the clock frequency of the generator 2 to turn on. .

Description

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The invention relates to radio engineering and can be used in asynchronous address communication systems.

The purpose of the invention is to increase the self-generated discrete-frequency signals.

The drawing shows a structural electrical circuit of the proposed device.

The device for generating optimal discrete-frequency signals contains a block 1 of high-frequency generators, a generator of 2 sync pulses, a first driver 3 numbers, a key 4, an adder 5 modulo (nt-1), a first decoder 6, an adder 7 modulo v, a second decoder 8, matrix permanent storage unit 9, multiplexer 10, storage register 11 of the source code sequence, the third decoder 12 and the second and third drivers 13 and 14 numbers.

The device works as follows.

In the initial state, the initial code sequence in the storage register 1 1 is written in binary code from the keys of the initial installation (not shown) sequence of decimal numbers from the segment of the natural row from 1 to v, and two randomly selected groups of memory elements are not allowed to be written equal decimal numbers, and the order of writing numbers to all v groups of memory elements of register 11 is arbitrary. In other words, in register 11, of the total number v, an arbitrary permutation of v decimal numbers from the natural row segment from 1 to v is written.

From the message source (the digital code YA of the message is not shown, as well as two digital codes y4 and ya, which, with the matrix method of specifying addresses, are the composite address of the asynchronous-address communication system correspondent. In accordance with the sync code y, y, and at all times the transmission of the discrete-frequency signal, the first shaper 3 numbers form the y number arriving at the input of the key 4, the second shaper 13 numbers form the number y r 1-sh, arriving at the input of the second decoder 8, the third shaper 14 numbers form the y number 0- (v-1), arriving at the first input of the adder 7 modulo v. The number n is equal to the number k

elements in the block used asymmetric block diagrams, and (n + 1) - a prime number. The number m is the number of basic blocks relative to the Abelian automorphism group of the used asymmetric flowchart. The number v is the total number of elements of the flowchart. In accordance with the number of the second, the decoder 8 selects one of the main lines of the matrix permanent storage unit 9 with a capacity of a decimal type in which the elements of the base unit of the asymmetric block diagram used are written. In the cycle with each clock pulse, coming from the generator 2 mshhroimpulu, key 4 delivers the number yj to the input of the adder 5 modulo (n + 1). Accumulated Amount

ui + 0 h (ilI,, ..

v k N k + y, mod (n + 1)

enters the input of the first decoder 6, in accordance with which the first decoder 6 selects one of the n columns of the matrix permanent storage unit 9 with a capacity of three decimal numbers. The number oi located at the intersection of the m-ft row and the n-th column from the output of the permanent storage unit 9 is fed to the second input of the adder 7 modulo v, from the output of which the calculated sum b cxL + mod v is fed to the address input of the multiplexer 10 The number b is the number of one of the v groups of memory elements of the storage register 11 of the original code sequence. The multiplexer 10 connects the memory cell group b to the input of the third decoder 12, which, in accordance with the decimal number stored in the selected group of memory elements (not indicated) of the register 11, includes one of the v high-frequency generators at the time determined by Generator clock frequency, 2.

The end of the transfer of a discrete-frequency signal corresponds to the arrival of the key 4 (n + 1) -th clock pulse on the control input, while in the adder 5 modulo (n + 1) the accumulated amount becomes zero

) 0 mod (n + 1), and at zero off during the first decoder 6 appears

signal log. 1, according to which in the first 3, second 13 and third 14 number generators, in accordance with the new numeric codes y, y and y, from the message source, new numbers y will be delighted | , y, y.

In the absence of messages from the source of messages, the decimal numbers y (, Y 2 and y3 on the power lines of the formers 3, 14 and 13 numbers are zero, the sum in the adder 5 modulo (n + 1) is equal to zero, the signal Log. 1 is present at the zero output of the first decoder 6, at both inputs of the adder 7 modulo v there are random numbers equal to zero. The decimal zero is present at the input of the third decoder 12, at the zero input of which (not shown) there is a signal from Log. 1, therefore all v high-frequency generators of block 1 high-frequency generators s off. In this case it is possible to implement an optimal system used shift discrete-frequency signals by .zapisi from initial setup key (not shown).

Claims (1)

Invention Formula A device for generating optimal discrete-frequency signals containing a block of high-frequency generators, the first number generator, the output of which is connected to the information input of the key, the output of which is connected to the input of a modulo ad (n + 1), the output of which is connected to the input of the first decoder, zero output which is connected to the control input of the first number generator and to the control input of the clock generator, the output of which is connected to the control input of the key, with 0 g 0 5 0 five 0 This information input of the first number generator is the first information input of the device, the outputs of which are the outputs of the high-frequency generator block, characterized in that, in order to increase the ensemble of discrete-frequency signals generated, two decoders, two number generators, modulo v, are entered matrix permanent storage unit, multiplexer and the storage register of the original code sequence, the outputs of which are connected to the information inputs of the multiplexer, the address input cat connected to the output of the adder modulo v, the first input of which is connected to the output of the matrix permanent storage unit, the first input of which is connected to the output of the first decoder, the zero output of which is connected to the control input of the second number-raiser and the control input of the third number-raiser, the output of which is connected to the second input of the adder modulo v, the output of the second number generator via the second decoder is connected to the second input of the matrix permanent storage unit, the output multiplexer It is connected to the input of the third decoder, the outputs of which are connected to the inputs of the high-frequency generator unit, while the information inputs of the second and third number generators are the second and third information inputs of the device, the fourth information inputs of which are the original code sequence.