SU748828A1

SU748828A1 - M-train generator

Info

Publication number: SU748828A1
Application number: SU782628743A
Authority: SU
Inventors: Владислав Николаевич Сухоносов; Анатолий Павлович Игонин; Владимир Николаевич Куприянов
Original assignee: Предприятие П/Я В-2962
Priority date: 1978-06-12
Filing date: 1978-06-12
Publication date: 1980-07-15

Description

Изобретение относитс к импульсной технике и может быть использовано в системах синхронизации, -передачи информации , измерени параметров движе- 5 НИН и других системах, формирующих шумоподобные сигналы, не требуюсцих вы .сЬкого быстродействи .The invention relates to a pulse technique and can be used in synchronization systems, transmission of information, measurement of the parameters of the movement of 5 NIN and other systems that form noise-like signals that do not require much speed.

Известен генератор М-последователь- ностей, содержащий генератор тактовых ю импульсов, п-разр дный регистр сдвига , обеспечивающий получение 4-х и более обратных св зей, при которых генерируютс М-последовательности, запоминающее устройство на п разр дов,|j сумматор по модулю два, устройство автоматического переключени обратных св зей, включенное между запоминающим устройством и регистром сдвига, содержащее схекы совпадени , управле-20 ни , задержки и логического ело- . жени 1.A generator of M-sequences is known, which contains a generator of clock pulses, an n-bit shift register, providing 4 or more feedbacks in which M-sequences are generated, a memory device for n bits, | j module two, an automatic feedback switching device, connected between the memory device and the shift register, containing the matching, control, delay, and logical body. wives 1.

Генератор характеризуетс .«ложностью построени , особенно дл .формировани всех возможных М-последова-25 тельностей и при больших значени х п.The generator is characterized by “falsity of construction, especially for the formation of all possible M-sequences and for large values of n.

Наиболее близким по технической сущности к предлагаемому вл етс генератор М-последовательностей, который содержит генератор тактовых им- QThe closest in technical essence to the present invention is the generator of M-sequences, which contains a clock generator named Q

пульсов, п-разр дный регистр сдвига, m сумматоров по модулю два и коммутатор , коммутатор содержит п многор дных групп переключателей. При включении одной или нескольких групп переключателей происходит соединение соответствующих выходов регистра сдвига со входами сумматоров и заземление остальных его входом. Номера включена; ных групп переключателей определ ютс позиционными номерами ненулевых коэффициентов полинома задержки, формирующем М-последовательность. Полином, имеющий максимальное число ненулевых коэффициентов, определ ет равное ему минимально- необходимое, число сумматоров дл фсррмировани всех возможных М-последовательностей. Набор любой из множества возможных комбинаций включенных групп производитс минимальным количеством органов управлени , равным п 2.pulses, an n-bit shift register, m modulo two adders and a switch, the switch contains n multi-groups of switches. When one or several switch groups are turned on, the corresponding outputs of the shift register are connected to the inputs of the adders and the others are grounded by its input. Rooms included; The switch groups are determined by the positional numbers of the nonzero delay polynomial coefficients forming the M-sequence. A polynomial having the maximum number of nonzero coefficients determines its minimum required number, the number of adders for ffrmirovany all possible M-sequences. A set of any of a variety of possible combinations of included groups is produced with a minimum number of controls equal to n 2.

Claims

The disadvantage of the known generator is that the number of switches of the switch and the connections between them is large and disproportionately increases with increasing number n, moreover, it is necessary to use a certain number of modulators. Two of them increase with increasing n, which reduces the reliability of the generator. The purpose of the invention is to increase the reliability of the generator of M-sequences. It is achieved by the fact that a generator of clock pulses, the output of which is connected to the clock input of the bit shift register, the modulator two, is additionally entered into an n-ring shift register, two elements OR, and three elements AND , the output of the first element OR is connected to the input of the n-bit shift register, the clocking inputs of which are connected to the output of the clock pulses, and the output connected to the first inputs of the first and second elements, And the second input of the second element a AND is connected to the output of the first bit of the ring shift register, to the first inputs of the modulo two adder and TpeTbeir-o of the AND element, the output of which is connected to the first input of the first OR element, the second input of which is connected to the output of the second AND element, while the outputs the switch is connected to the inputs of the second element OR, the output of which is connected to the second input of the first element AND, the output of the first element AND is connected to the second input of the modulo two adder, the output of which is connected to the second input of the third element AND, and the third input about-; Modulo two is connected to the output of the clock generator. In the drawing, the functional diagram of the M-sequence generator is represented. The generator contains the generator I of such pulses, n-bit register 2. shift, ring register 3 shift, switch 4, elements 5, 6, 7 AND, elements 8, 9 OR, adder 10 across the module two) performed on the element AND AND OR, elements 12, 13 AND and the D-trigger 14. The general principle of operation of the device is to deploy at the time of formation of one character M-sequence of the preceding delayed characters in a temporary chain and successively modulo two characters, whose positions coincide with the time positions of logical second sequence synchronous with it. This second sequence consists of and O, whose temporary positions correspond to the position of nonzero and zero coefficients in the delay polynomial, represented in binary form. The device operates as follows. Before starting work, all resolutions of register 3, except the first (youngest), are recorded on O, and, for example, in all bits of register 2 .-, Adder 10 is in the state. Switches switch 4, the numbers are equal to the position ngo. measures of nonzero delay polynomial coefficients, closed. The values of the first in the nth position of register 2 correspond to the values of the delayed one to n clock ticks of the pseudo-random sequence symbols. When the clock pulses from the generator 1 to the clock inputs of registers 2 and 3, at the output of the register 2 appear, starting; From the nth number, the symbols and arrive at the inputs of elements 5 and 6 I. The inverse control input of element 6 and the signals from the output of register 3 do not pass during the first n cycles, therefore it is open for passing symbols at this time. From the output of element 6 AND, the characters arrive at the first input of element 8 OR, and then from the output of the last - and input to register 2. After -p cycles, register 2 returns to its original state. Simultaneously with the considered progress of the characters, it moves through register 3, each clock stroke appears on one of its outputs and interrogates the switch 4 connected to it. In the case of a closed switch, this is passed to the input of element 9 OR, which performs the function of assembling the output signals switch 4, then from the output of the element 9 OR enters the control input of the element 5 AND and opens it. As a result, the corresponding symbol from the output of element 5 I passes to the counting input of the adder 10. Through n clock cycles on the adder 10, a new symbol of a pseudo-random sequence is formed. In the next n + 1 cycle of operation of the device, the output of the register 3 enters the inverse control input of the element bI, the control input of the element 7 and the inputs of the element 11 OR and the element 13 And the adder 10, as a result, the element 6 And closes and does not pass The input to the register is the 2nd nth character, which is thus erased. Element 7 And opens, and a new character from its output goes to the second input of element 8 OR, next with the last input, to write to the first digit of register 2, in which under the action of the n-1 tact pulse, its shift occurs right one bit. The adder-10 is reset to the zero state. Logic returns to the first bit of register 3 and the cycle of forming a single character of the sequence ends, and then the device repeats itself over the considered cycle. With this particular implementation of the adder 10 modulo two, the generator operates as follows. From the 1st to the right clock cycle, inclusively, the inverse input of the element 13 And there is a logical o, after which the D-trigger 14 operates in the counting mode, modulo two information arriving at its sync input from the output. element 12 I. At the first input of element 12 I, clock pulses from generator 1 are sent, and at its second input, the characters arrive through element 5 AND and element 11 OR from the output of register 2. At the n + 1 clock cycle from the output of register 3 it enters 1 the inverted control input of element 6 AND, to the control input of element 7 AND and to the inputs of elements 11 OR-and -13 AND of the adder 10. As a result, the element b And closes the contents of the older (1 - n) register and 2; element 7A opens and the result of summing up on preceding steps, fnew symbol of the sequence) is rewritten from the output of the D flip-flop 14 via element 7 of the AI element 8 OR for the first register bit 2; D-trigger 14 is reset to the zero state. Thus, the generator returns to the initial state of the next pseudo-random symbol generation cycle. Claims An I-Sequence Generator containing a clock pulse generator, the output of which is connected to the tax input of the discharge shift register, a modulo two adder, characterized in that, in order to increase the reliability of the generator, the n-ring shift register is added to it, two OR elements and three AND elements, the output of the first OR element is connected to the input of the n-bit shift register, the clocking inputs of which are connected to the output of the pulse generator, and the output is connected to the first the inputs of the first and second elements And the second input of the second element And is connected to the output of the first paEr yes ring. (shift register, to the first inputs of the modulo two adder and the element I, the output of which is connected to the first: the input of the first element OR, the second input of which is connected to the output of the second element AND, while the outputs of the switch are connected to the inputs of the second element OR, output which is connected to the second input of the first element And, the output of the first element And is connected to the second input of the modulo two adder, the output of which is connected to the second input of the third element And, and the third input modulo two is connected to the output of the clock pulse generator Sources of information taken into account during the examination 1. Authorship certificate of the USSR W 301834, class H 03 K 3/84, 8.05.69.

2. USSR author's certificate number 3.75769, cl. H 03 K 3/84, 04.19.71.

748828