JPS56146322A - Frequency multiplying device - Google Patents

Frequency multiplying device

Info

Publication number
JPS56146322A
JPS56146322A JP4980180A JP4980180A JPS56146322A JP S56146322 A JPS56146322 A JP S56146322A JP 4980180 A JP4980180 A JP 4980180A JP 4980180 A JP4980180 A JP 4980180A JP S56146322 A JPS56146322 A JP S56146322A
Authority
JP
Japan
Prior art keywords
signal
input signal
registers
bit
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4980180A
Other languages
Japanese (ja)
Inventor
Junichiro Yamada
Satoru Kojima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4980180A priority Critical patent/JPS56146322A/en
Publication of JPS56146322A publication Critical patent/JPS56146322A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass

Abstract

PURPOSE:To obtain a frequency-multiplied signal of input signal from an optional stage of a shift register, by applying the clock corresponding to the necessary multiplied frequency to the shift register to which the pattern of input signal is preset. CONSTITUTION:The outputs of 8-bit shift registers 2b, 2d, 2f and 2h among the registers 2a-2h are inverted by inverters 6a-6d and then applied to the reset direct terminals of D type F.F1a-1d, respecively. When input signal DI is applied to the clock terminal of F.F1a, the signals having different levels with every bit are reset to the shift registers 2a and 2b through their parallel preset input terminals. In this case, F.F1a is reset, and thus the registers 2a and 2b are set in the serial mode to transfer the signal having different levels with every bit and synchronously with the clock pulse CPI. As a result, the output signal D01 having an 8-multiplied frequency compared with the input signal DI can be obtained from the final stage of the register 2b. After this, the output D0 having an 8<4>-multiplied frequency is obtained in the same way.
JP4980180A 1980-04-15 1980-04-15 Frequency multiplying device Pending JPS56146322A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4980180A JPS56146322A (en) 1980-04-15 1980-04-15 Frequency multiplying device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4980180A JPS56146322A (en) 1980-04-15 1980-04-15 Frequency multiplying device

Publications (1)

Publication Number Publication Date
JPS56146322A true JPS56146322A (en) 1981-11-13

Family

ID=12841242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4980180A Pending JPS56146322A (en) 1980-04-15 1980-04-15 Frequency multiplying device

Country Status (1)

Country Link
JP (1) JPS56146322A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009044209A (en) * 2007-08-06 2009-02-26 Kyosan Electric Mfg Co Ltd Digital frequency multiplication circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009044209A (en) * 2007-08-06 2009-02-26 Kyosan Electric Mfg Co Ltd Digital frequency multiplication circuit

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