JPS56140722A - Noise eliminating circuit - Google Patents

Noise eliminating circuit

Info

Publication number
JPS56140722A
JPS56140722A JP4267480A JP4267480A JPS56140722A JP S56140722 A JPS56140722 A JP S56140722A JP 4267480 A JP4267480 A JP 4267480A JP 4267480 A JP4267480 A JP 4267480A JP S56140722 A JPS56140722 A JP S56140722A
Authority
JP
Japan
Prior art keywords
noise
signal
clock pulse
input signal
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4267480A
Other languages
Japanese (ja)
Inventor
Toshiyuki Nakao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4267480A priority Critical patent/JPS56140722A/en
Publication of JPS56140722A publication Critical patent/JPS56140722A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference

Abstract

PURPOSE:To eliminate the noise in accordance with the variation of the noise width and without using any analog process, by comparing the past transmission signal stored temporarily with the present transmission signal to decide whether the signal inversion is due to the noise or not. CONSTITUTION:The delayed flip-flop 4 stores temporarily the input signal 1 with the next clock pulse and then applies the output 4' to the state comparison logic circuit 6. The circuit 6 compares the input signal 1 during the one-preceding clock with the present input signal 1 in terms of the state and then applies the signals 7' and 8' contrary to each other to the next stage, and then shifts the waveform inverted by the noise at and after the breaking point of the clock pulse to apply it to the delayed flip-flop 5. The flip-flop 5 supplies the arithmetic result signal 9' synchronously with the next clock pulse 2 and accordingly eliminates the noise equivalent to one clock pulse. Then the input signal is restored and the output signal 3 is supplied.
JP4267480A 1980-03-31 1980-03-31 Noise eliminating circuit Pending JPS56140722A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4267480A JPS56140722A (en) 1980-03-31 1980-03-31 Noise eliminating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4267480A JPS56140722A (en) 1980-03-31 1980-03-31 Noise eliminating circuit

Publications (1)

Publication Number Publication Date
JPS56140722A true JPS56140722A (en) 1981-11-04

Family

ID=12642571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4267480A Pending JPS56140722A (en) 1980-03-31 1980-03-31 Noise eliminating circuit

Country Status (1)

Country Link
JP (1) JPS56140722A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0281313A2 (en) * 1987-03-03 1988-09-07 Advanced Micro Devices, Inc. Digital receive filter circuit
US7380192B1 (en) * 1999-03-09 2008-05-27 Iroc Technologies Logic circuit protected against transient disturbances

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0281313A2 (en) * 1987-03-03 1988-09-07 Advanced Micro Devices, Inc. Digital receive filter circuit
US7380192B1 (en) * 1999-03-09 2008-05-27 Iroc Technologies Logic circuit protected against transient disturbances

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