JPS54143031A - Driving control system of shift register circuit - Google Patents

Driving control system of shift register circuit

Info

Publication number
JPS54143031A
JPS54143031A JP5163978A JP5163978A JPS54143031A JP S54143031 A JPS54143031 A JP S54143031A JP 5163978 A JP5163978 A JP 5163978A JP 5163978 A JP5163978 A JP 5163978A JP S54143031 A JPS54143031 A JP S54143031A
Authority
JP
Japan
Prior art keywords
circuit
pulse
complementary
phi3
established
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5163978A
Other languages
Japanese (ja)
Inventor
Masataka Hirasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5163978A priority Critical patent/JPS54143031A/en
Publication of JPS54143031A publication Critical patent/JPS54143031A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287Organisation of a multiplicity of shift registers

Abstract

PURPOSE:To reduce consumption power by forming a positive feedback loop dependent upon complementary inversion circuit for a storage circuit and stabilizing the data holding of a storage means when the frequency of each pair of complementary clock pulses in sequential operations is lowered. CONSTITUTION:Input data selection circuit 30, storage circuit 20 where shift registers 211...21N are connected continuously, control pulse generator circuit 70 which generates control pulses to shift successively data in circuit 20, and command control signal generator circuit 60 which controls the oeration of circuit 70 by commands are provided. In circuit 20 of this constitution, the first and the second complementary MOS inversion circuits which are driven by a pair of the first and the second complementary clock pulses phi1 and phi2 and the third complementary MOS inversion circuit which is driven by the third complementary clock pulse phi3 are provided, and further, feedback circuit 23 which feeds back the output if circuit 20 to circuit 30 positively is provided. then, the system is so constituted that pulse phi1 may be established durisng the non-establishment period of the second pulse phi2 as well as the third pulse phi3 and pulse phi3 may be established after pulse phi2 is established.
JP5163978A 1978-04-28 1978-04-28 Driving control system of shift register circuit Pending JPS54143031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5163978A JPS54143031A (en) 1978-04-28 1978-04-28 Driving control system of shift register circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5163978A JPS54143031A (en) 1978-04-28 1978-04-28 Driving control system of shift register circuit

Publications (1)

Publication Number Publication Date
JPS54143031A true JPS54143031A (en) 1979-11-07

Family

ID=12892406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5163978A Pending JPS54143031A (en) 1978-04-28 1978-04-28 Driving control system of shift register circuit

Country Status (1)

Country Link
JP (1) JPS54143031A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5677991A (en) * 1979-11-28 1981-06-26 Hitachi Ltd Shift register circuit
JPS5750391A (en) * 1980-09-10 1982-03-24 Toshiba Corp Two-way shift register
US5268596A (en) * 1990-11-27 1993-12-07 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for latching data around a logical data processor
US5321399A (en) * 1992-05-18 1994-06-14 Mitsubishi Denki Kabushiki Kaisha Parallel/serial conversion circuit, serial/parallel conversion circuit and system including such circuits

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5294741A (en) * 1976-02-04 1977-08-09 Citizen Watch Co Ltd Shift register
JPS5315720A (en) * 1976-07-28 1978-02-14 Nippon Telegr & Teleph Corp <Ntt> Static shift register

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5294741A (en) * 1976-02-04 1977-08-09 Citizen Watch Co Ltd Shift register
JPS5315720A (en) * 1976-07-28 1978-02-14 Nippon Telegr & Teleph Corp <Ntt> Static shift register

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5677991A (en) * 1979-11-28 1981-06-26 Hitachi Ltd Shift register circuit
JPS5750391A (en) * 1980-09-10 1982-03-24 Toshiba Corp Two-way shift register
JPS624799B2 (en) * 1980-09-10 1987-01-31 Tokyo Shibaura Electric Co
US5268596A (en) * 1990-11-27 1993-12-07 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for latching data around a logical data processor
US5321399A (en) * 1992-05-18 1994-06-14 Mitsubishi Denki Kabushiki Kaisha Parallel/serial conversion circuit, serial/parallel conversion circuit and system including such circuits

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