SU1465985A1 - Pulse width modulator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in key low frequency amplifiers, secondary power sources, collector modulators of transmitters. The purpose of the invention is to increase the reliability of the modulator by reducing the switching frequency of the output stage while maintaining the accuracy of the input signal conversion. The pulse width modulator contains a generator of 1 clock pulses, a counter of 5 pulses, RS-flip-flop 2. Introduction of RS-flip-flop 7, AND-NE elements 3, 4, and coincidence element 6 ensured the formation of one two-way symmetric width-modulated signal from two samples of the input signal in the interval equal to two periods of the strobe pulses. This allows, without compromising the accuracy of conversion of the input signal, to halve the switching frequency of the output stage of the modulator, which leads to increased reliability. 1 il. (L

Description

The invention relates to a pulse technique and can be Used in key low frequency amplifiers, secondary power supplies, collector transmitter modulators.

The purpose of the invention is to increase the reliability of the device by reducing the switching frequency of the output stage while maintaining the accuracy of the conversion of the input signal.

The drawing shows a functional diagram of a pulse-width n

module a.

Pulse-width modulator with; Lit generator 1 clock: pulse: s ,. RS-trigger 2., IrNE 3 elements,, 5 pulse counter, mastering element 6, RS-trigger 7, while • the strobe-pulse code bus is connected to the input, recording of the 5-pulse counter and s-input · RS-trigger 2, the R-input of which is connected to the output of the coincidence element 6, and the output - to the first inputs of the AND-NOT elements 3, 4, the second inputs of which are connected to the output of the Clock Generator 1, and the outputs - to the inputs of the forward and backward counts of counter 5, respectively , the information inputs of which are connected to the input digital (Y-1) ~ th bit pin, and the outputs are: full input element rows 6 'with the D-coincidence with

respectively, the output of which is the third input and the R- and S-inputs of the RS-flip-flop 7 <; ^ in is with the output bus house 'of the AND-NOT 4 element and the third inverse input of the AND-NOT 3 element ”

Pulse-width modulator operates as follows.

Suppose the RS trigger 7 is reset. The clock generator 1 generates a signal with a frequency of if. With the arrival of the strobe pulse, information is recorded in the counter 5 t of the input (NI) and bit bus and the RS trigger 2 is set to the state ^!, 1 ”“ The signals from the outputs of the RS triggers and 7 allow the signal to pass from the 1 pulse generator through element AND NOT 3.to the input of the direct counter of the counter. 5 “Counter overflow for 5 _hours. It occurs after a time inversely proportional to the value of the input code written into it. The signal · from the second output (direct overflow) of the counter 5 sets the RS-trigger 7 in the state ”1. having completed the pause formation, it overturns the RS-trigger 2 through the coincidence element 6, the level O signal from the output of which prohibits the further passage of the signal of the clock generator 1 through the AND-NOT 3, 4 elements to the counter inputs 5. 0 by the arrival of the next strobe information is written to counter 5 and the RS-trigger 2 is installed, but now the signals from the outputs of the RS-triggers 2 and 7 allow the signal to pass from the clock generator 1 through the AND-NOT 4 element. counter counter input 5. Counter overflow in this case will occur after a time directly proportional to the value of the input code recorded in it. In this case, the signal from its first output (reverse overflow) will reset the RS-flip-flop 7, completing the formation of the pulse, and through the element 6 matches overturn RS-flip-flop 2, the output signal of which. prohibits the passage of the signal. generator 1 clock pulses through the elements AND NOT 3, 4.

The frequency of the output signal of the generator 1 'is determined by the ratio f Tf = N / TST - t _C i,

'D6 N - maximum code input go signal; t CHLR - pulse repetition period; strobe t smiling - official time necessary ' Dim to prepare the device for work.

Thus, the introduction of new elements and connections into the pulse-width modulator provided the formation of one bilateral symmetric pulse-width-modulated signal from two samples of the input signal over an interval equal to two strobe periods. This allowed, without compromising the accuracy of the input signal conversion, to halve the switching frequency of the modulator output stage, which, in turn, increased the reliability of the device, and when using the modulator in key low-frequency amplifiers, it reduced the distortion of the low-frequency signal.

Claims (1)

Claim A pulse-width modulator containing a clock pulse generator, a pulse counter, the information inputs of which are connected to the input digital (Y-1) -th bit bus, the recording input is connected to the input bus of the strobe pulse, and the first overflow output is to the R-input of the first RS-flip-flop, the output of which is connected to the output bus of the modulator, characterized in that, in order to increase reliability, it additionally introduces a second RS-flip-flop, two NAND elements and a coincidence element, the first input of which is connected to the R input of the first RS-flip-flop , the second entrance - with S - the input of the first RS-trigger and the second output of the pulse counter overflow, and the output - with the R-input of the second RS-trigger, the S-input of which is connected to the input bus of the strobe pulse, and the output - with the first inputs of AND-NOT elements, the second inputs which are connected to the output of the clock generator, and the outputs with the inputs of the forward and reverse counts of the pulse counter, respectively, while the output bus of the modulator is connected to the third input of the second AND-NOT element and the inverse third input of the first AND-NOT element.