SU1608776A1 - Device for controlling d.c. motor - Google Patents

Abstract

The invention relates to electrical engineering and can be used in digital systems for automatic control of DC electric drives with pulse-width converters. The purpose of the invention is to increase reliability by eliminating the through-current mode. The introduction of the digital delay node and the control pulse generator eliminates the possibility of through-current flow, since the control pulses fed to the emitter-base transitions of the transistor switches of the bridge reverse transistor pulse-width converter do not overlap, and the duration of dead-end pauses can be set optimal. In addition, this device allows one pulse generator to be used both to fill the reversible counter and to form a pulse width modulation period, which increases the reliability of the device. 6 Il.

Description

The invention of electrical engineering f may be used in digital. Electr: automatic control systems with a pulse width converter converter. The purpose of the invention is to increase reliability due to the exclusion of the through mode

current,

H diagram

FIG. Figure 1 shows a structural device for controlling a DC motor; FIG. 2 is a functional diagram of a digital delay node; in fig. 3 is a functional diagram of a control pulse generator; FIG. 4 is a functional diagram of a code converter; yo time interval; in Fig. 5, a functional; on a bridge circuit, a transistor pulse-width converter; in fig. 6 - time diagrams of the device operation with NBX O (a) and Nnx O (b). The device for controlling a direct current electric motor comprises a pulse generator 1, the output of which is connected to the first and third inputs of the digital delay section 2, respectively, and a code converter 3 in the time interval, the second input of which is combined with the second input of the digital delay node 2, the second input of the pulse driver 4 control and is connected to the bus. Initial installation. The first input of the converter 3 of the code in the time interval is connected to the second output of the control code register 5, the input of the control code register 5 in

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ON

bus Record, and its information inputs - the corresponding control code buses, the first output of the control code register 5 is connected to the first input of the distributor 6 pulses, the second input of which is connected to the first output of the driver 4, the first control pulses, and the first, second, third and fourth outputs the distributor 6 pulses are connected to the corresponding inputs of the bridge transistor pulse-width converter 7. The first and third inputs of the driver 4 control pulses are connected respectively to the outputs of the 3, the forming of code in the time interval and the digital delay unit 2, to the third input of which is connected a second output of the 4 control pulses.

The digital delay node 2 (Fig. 2) contains, for example, three logic elements 2I-NOT 8-10, logic element 2ILI 11, three logic elements 2I 12-14, trigger 15, subtractive counter 16, inverter 17, control voltage 18 at the output of the trigger 15, the voltage 19 at the output of the subtracting counter. 16, the pulse sequences 20 and 21 from the outputs, respectively, of the elements 2I – HE 9 and 10.

Shaper 4 control pulses (Fig. 3) contains two inverters 22 and 23, four logical elements 2И-НЕ 24-27, four quad reger 28-31, sequences of width-modulated pulses 32 and 33 arriving at the first input of the former 4 control pulses, four pulse sequences 34-37, formed on the principle of sequential control at the direct outputs, respectively, of the flip-flops 28-31.

Converter 3 codes in the time interval (Fig; 4) contains inverters 38 and 39, logic elements 2И 40-42, logic element 2И-НЕ 43, logic element ЗИ-НЕ 44, triggers 45 and 46, reversible counter 47. control voltage 48-50, respectively, on the summing, subtracting, and resolution inputs of the recording of the reversible counter 47, the sequence 51 and 52 of control pulses on the direct outputs, respectively, of the flip-flops 45 and 46, and the value of the code 53 on the output of the reversible counter 47.

The bridge reversing transistor pulse-width converter 7 (Fig. 5) contains four transistor switches TK1-TK4 54-57, an electric motor 58 DC, a control voltage 59-62 transistor switches, respectively TK1-TK4, the output voltage 63 of a bridge reversing transistor 0

pulse width converter 7 at the input of the DC motor 58.

The device works as follows.

In register 5 of the control code, the code of the control signal NBX is applied to the input of the control unit of the electric motor of the direct current motor, which

converted into pulse width modulated pulses. The sign of the control code is stored in the high order, while the remaining bits contain the module of the number in the forward code. Writing a code into register 5 of the control code is carried out when a positive differential pulse is written across the write bus to its input. The maximum possible value of the control code that the device converts is determined as follows: INKI 2 -1 -Kz, where Kz is the value of the time delay code, which is determined by the time t3 of absorption of excess media in the base of the disconnecting transistor switch and

pulse freH frequency from impulse generator 1: K3 t3freH; gp is the size of the register 5 control code. In this case, the period of the width-modulated signal is determined by:

jn - 1

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we pitch

fr

The code converter 3 into the time interval converts the control code module I Nexl Mshim + Kz into two sequences of pulse-width modulated pulses, which are fed to the input of the driver 4 of the control pulses. At the second input of the driver 4 pulses

Two sequences of pulses of duration 13 from node 2 of the digital delay are received. Shaper 4 control pulses forms four sequences of width-modulated

impulses required to implement alternately controlling transistor switches of a bridge reversing transistor pulse-width converter 7. Pulse distributor 6 realizes reversible control by switching keys of a bridge reversing transistor pulse-width converter 7 depending on the sign bit arriving at its first input

control code from the first output of the register 5 control code. The digital delay node 2 generates two sequences of time delay pulses of duration 13 7 -which are used when

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peHocja chik

of the four forms of pulsed after-control KOtoptix pulses are separated in time by

The epatop 1 pulse is designed to form the sequence of stable freH frequencies necessary for clocking the device operation.

When a pulse arrives on the bus, the initial setup (fig. B) with its front edge is the zero-down counter 47, the logical 0 is written into the trigger 15.28,30.45.45 and 46, the logical 1 is written into the riggers 29 and 31, and also recorded Kz code in the subtractive counter 16, node 2 digital delay. At the same time, the first, second, third and fourth inputs of the pacnf of the 6 pulses are received by the signals J4-37, respectively, and from its outputs by the ynpai voltage 59-62 (fig.b) are transmitted to the transistor switches TK1-TK4 of the bridge transistor pulse-width converter 7. A high level signal from the inverted output of the PS 46 flip-flop by the end of the pulse on the bus. The initial setting allows the passage of the freH pulses from the generator 1 imp; On the subtractive input of the reversing one (of the ruler 47. Since the reversible counter 47 operates on the subtraction and the zero code is recorded in it. A reverse impulse is formed at its reverse transfer output. This impulse into the reversible counter creates the iNexl code installed on its information inputs .

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In addition, the transfer momentum of the entrance to the installation to the unit state of the zigger 46 and changes its state, the home element 44 closes and starts

element 43. In this case, the pulse-frequency freH from the generator 1 of the pulses arrives at the summing input of the counter 47. In addition, the signal: oky level through the open element goes through the inverter 23. the rotor 31 is set to the zero state and a high level is applied to first) of item 26. Up to this point, node 2 of your delay does not participate in, since valve 8 is closed. When the flip-flop of the trigger 31 is in the zero state, the element 14 and the high pass signal through the logical element 11. Writes logical 1 to the trigger and opens the element 8, allowing the passage of clock pulses from 1 pulses to the counting input 0 of the counter 16. set-NOVL0N code KZ.

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When the zero code is fixed on the subtractive counter 16, a transfer pulse 19 is formed at its reverse transfer output, which enters through the open element 12 to the input of the subtractive counter 16, and also resets the trigger 15 to the zero state. Thereby, from the direct output of the trigger 15 through the open element 9, pro; having inverted, through time gz, the second input of element 26 receives a high level signal. At the same time, a low level signal arrives at the installation input into the unit of trigger 30, and the trigger 30 is set to one. Element 14 is closed by a low level signal from the inverse output of the trigger 30. In this case, the inputs of logic element 2ILI 11 have low level signals, and a low level signal from its output prohibits the passage of clock pulses through element 8. Node 2 digital delay is again turned off .

The summation in the reversible counter 47 continues until the appearance of an overflow pulse from its overflow output. This pulse writes the value of the INaxI code to the reversible counter 47. It switches the trigger 46 to the zero state, thereby switching the pulse generator 1 from the summing to the subtracting input of the reversing counter 47, and switches the trigger 45 operating in the counting mode to a new (single) state the The low level signal from the direct output of the trigger 46 closes the elements 41 and 42, while the low level from the output of the element 42 is reset to the O trigger 30, and a high level enable signal is set at the first input of the element 27. At this point, the digital delay node 2 is activated.

At the output of element 14, a high level signal appears, which, similarly to that described, sets trigger 15 into one state and permits the passage of pulses from pulse generator 1 through element 8 to the counting input of the subtracting counter 16. Thus, trigger 15 is held in unit state time t3 K3 / freH, and there is a high level signal at the second inputs of elements 9 and 10. The high level signal at the first input of the element 9 is saved, and consequently, at the output of the element 9 there is a low level signal that prohibits the switching of the trigger 31 to one state,

Thus, the triggers 30 and 31 are in the zero state for the time t3. When fixing the zero co.da in the subtracting counter 16, the pulse from its reverse transfer output switches the trigger 15 and overwrites the code Kz into the subtractive counter 16. In this case, the second input of the element 27 is set to a high level signal and the trigger 31 is not switched to one state. Thus, turning on trigger 31 after turning off trigger 30 occurs with a delay of 1h. It is from these triggers that the control pulses through the distributor 6 pulses arrive at the transistor switches of one vertical of the bridge reversing transistor pulse-width converter 7.

. When fixing.in the reversible counter 47 zero code at its output reverse transfer formed a transfer pulse. This impulse to the reversible counter 47 makes the next recording of the code I MVh I. arriving at its information inputs from the second output of the register 5 of the control code. In addition, the transfer pulse enters the setup input to the unit state of the trigger 46. The high level signal from the direct output of the trigger 46 allows the clock pulses from the pulse generator 1 to pass through the element 43 to the summing input of the reversing counter 47, and the low level signal from the inverse output trigger 46 prohibits them from passing through element 44 to the subtracting input of reversible counter 47. In addition, high level signal 52 through open element 41, having passed through inverter 22, sets trigger 29 to the zero state and a high level is applied to the first input of the element 24. But the trigger 28 is not turned on, since at the second input of the element 24 a low level signal from the output of the digital delay node 2 is set.

At the time of switching trigger 29 in

a zero state. Both inputs of element 13 receive high-level signals from inverse outputs of flip-flops 28 and 29. Logic 1 from output of element 13, having passed through logic element 2ILI 11, writes logical 1 to trigger 15 and opens element 8, thereby allowing the passage of clock signals. pulses to the counting input of the subtracting counter 16, in which the code Kz is fixed to this moment. Processes

in node 2, the digital delays proceed as described. At time t3 after turning off the trigger 29, the second input of the element 24 receives a high level signal from the digital delay node 2 and the trigger 28 switches to the one state, and the digital delay node 2 turns off from

operation until one of the included triggers is turned off (triggers 28 and 31).

The summation in the reversible counter 47 continues until the appearance of a pulse

overflow from its overflow output. This pulse writes the value of the INexl code to the reversible counter 47, switches the trigger 46 to the zero state, thereby switching the pulse generator 1 with

0 summing to the subtracting input of the reversible counter 47, and switches the trigger 45 to a new (zero) state. In this case, signals from the direct and inverse outputs of the trigger 45 close element 41 and open element 42. At the output of elements 41 and 42, low-level signals from the direct output, trigger 46, pass.

The low level signal from the output of the element 41 is reset to the O trigger 28 (in this case

0 the digital delay unit 2 is switched on), and the high-resolution enable signal is set at the first input of the element 25. At its second input, the high level signal from the output of node 2 is digitally delayed via WT1z and trigger 29 is set to one by a low level signal at its setting input to one state. At this moment all elements of the described part of the scheme came in

0 The condition considered earlier. Reversible counter 47 now works on subtraction. Further work of the described part of the scheme is repeated and proceeds similarly.

5 Thus, at the output of the driver 4 of the control pulses, four sequences 34-37 of pulse-width modulated pulses are formed, which are formed according to the principle of sequential control.

0 With a certain sign in; 5: one NBX signal, control pulses 59 and 62 duration, .. .. t-., NmMM f ti (1 + yj Gshim, where in 1 WIM freH is the relative duration of connection of the electric motor 58 direct current to the power source, - are fed to diagonally located transistor switches (TK1, TK4) with a shift by half a period (Fig. 6), and the control pulses 60 and 61 with a duration of 12 (1-) Tshim are also shifted on the paliper, they are fed to the transistor switches of the opposite diagonal (ТК2, ТКЗ), In this case, the interval 58 second current source connected to the power via diagonally arranged keys, as the interval (the load (Gusteau direct current motor 58) is short-circuited via the upper or lower

five

transistor keys. When the sign of the input signal NBX changes, the order of control of diagonally located transistor switches is changed by the distributor 6 pulses to the opposite. By alternately controlling the dc electric motor 58, sign-on-cI pulse pulses of a duration that is proportional to the signal at the input of the NBX are formed.

Thus, the application of the proposed device in digital systems of automatic control of electric drives P1) allows converting control codes into a duration of Il1puls, the modulus of which changes from ot 0 to 2n-1-Cs. The total number of possible values of the output signal is determined by the width of the p-B1FUCH counter and is 2. At the same time, all four t of the anisistor key of the bridge transient from the current pulse-width converter are found in the switching state however, the switching frequency of each of them is two times less than the frequency of the output voltage. The controllers on the (, yarns of transistors of one phase) of the bridge TKG, TKZ and TK2. TC4 is constantly out of phase. in this case, the transponder keys are switched through a period of output voltage 2 Tshim. This achieves the same operating conditions of semiconductor devices in the circuit of a bridge reversible transistor pulse-width converter.

Increased reliability of the device is also ensured by the fact that f. The latitude of the width-modulated 1 / mpulse and the period of the CME are formed on the reversible counter 47 from one pulse generator 1, thereby eliminating the additional synchronization circuit.

Analysis of timing diagrams (Fig. 6) shows that in practical use of t AI device control pulses, the emitter-base transitions of the transistor switches of the bridge reversing transistor pulse-width converter do not overlap at the moment of switching, while the duration (of the current pauses can in each case be set optimally (taking into account the resorption time of excess carriers in () the nuts of the switchable transistor switches, determined by the type of

transistors) by adjusting the time t3 (the value of Cs in node 2 of the digital delay is set by jumpers). This allows for the efficient elimination of the through currents 5 and thus provides an increased reliability of the device for controlling the DC motor.

Claims (1)

10 claims A device for controlling a direct current electric motor, containing a control code register, a motor 15 reversing transistor, a pulse-width converter, the output diagonal of which is intended to be connected to the core winding of a DC motor, a pulse generator, a code converter time interval, pulse distributor, the input of the control code register entry is a bus Record, the information inputs of the control code register are the corresponding 25 unit code buses The first output of the control code register is connected to the first input of the pulse distributor, whose outputs are connected to the corresponding inputs of a bridge reversing transistor pulse-width converter, the second output of the control code register is connected to the first input of the code converter in the time interval, the third input of which is 35 Connected to the output of the pulse generator, characterized in that, in order to increase reliability by eliminating the through-current mode, a pulse shaper is introduced into it. In this case, the digital delay node 40, the first input of which is connected to the output of the pulse generator, the second inputs of the control pulse generator, the digital delay node and the code converter in time interval 45 are combined and connected to the bus. The initial setting and the third part of the digital delay node are connected to the second output of the digital delay generator. control pulses, the first output of which is connected to the second input 50 of the pulse distributor, the output of the code converter in the time interval and the output of the digital delay node are connected respectively to the first and the third input of the control pulses. Y5 Sign% dk 4ffl  1 C /% / .. LU J3 t fui. one .m ll bft tsitf I laglcjc five "Y Jtv "M : 2t . a 1 o eg; c 5 Co  five h | and  Jl f pi 49 % tf, Kf tg fi-shch / ffuiuMMOg SHSHSHSHSHSHSHSHSHSHSHS., SHSHSHSHSHSHSHSHSHSHSHS -innnnii-j “D f 18 to t1 34 t Sh. fi-shch / ffuiuMMOg shshgshshshk t ... in П П П П i, J: Ihl Jl Jil P P