SU1287255A1 - Pulse sequence generator - Google Patents

Abstract

The invention relates to the etulent technique. It can be used in control systems. The aim of the invention is to expand the functional possibilities by forming a pulse sequence with a frequency that is inversely proportional to the supplied code. The device contains a generator 1 with a pulse frequency f, element And 2, RS-flip-flop 4, reversible pulse counter 3, input data bus 10. To achieve the goal, control unit 6, inverter 7, element And 7, element OR 9, are formed new functional relationships. When switching modes of operation, the input signal goes to the summing and to the subtracting inputs of the reversing pulse counter 3, resulting in the following: a pulse sequence with the number of pulses in the packet corresponding to the code of the recorded number A - at one output of the device, {mpuls, whose duration equal to the duration of the pulse sequence of the first output, on the other, or pulses with a partial sequence ff, / A on the third output of the device. 1 il. (L

Description

The invention relates to a pulse technique and can be used in control systems.

The aim of the invention is to enhance the functionality by forming a pulse sequence with a frequency that is inversely proportional to the supplied code.

The drawing shows the functional diagram of the pulse trainer.

The device contains a generator 1 with a pulse repetition frequency j, an element AND 2, a reversible pulse counter 3, an RS trigger 4, a generator 5 with a pulse frequency f, a control unit 6, an inverter 7, an element AND 8, an element OR 9, an input data bus 10.

The output of the generator 1 is connected to the first inputs of the elements AND 2, 8 Vigbd control unit 6 is connected to the second input of the element AND 2 and through the inverter 7 to the second input of the element And 8, the output of which is connected to the input of the summation of the reversible pulse counter 3, the input of which read is connected to output element AND 2. The generator 5 output is connected to the setup input of the RS-flip-flop 4, the preset input of which is connected to the output is less than zero reversible pulse counter 3, the overflow output of which is connected to the first input of the element OR 9, the second input d is connected to inverst you to exit RS-flip-flop 4, a direct output of which is connected to the third input of AND 2. The output of OR 9 connected to the input recording pulses down counter 3, Inforga mation whose inputs are connected to the input data bus 10

The device works as follows.

At the initial moment of time, depending on what the control signal is, permission will be given to the passage of pulses from the generator 1 either through the AND 2 element or through the AND 8 element.

If the control signal corresponds to the logical unit and the output of the RS flip-flop 4, connected to one of the inputs of the element 2, is also the state of the logical unit, then the element 2 is opened and its output pulses

0

five

five

0

five

five

0

five

From the output of generator 1, they are fed to the subtracting input of the reversible pulse counter 3. These pulses successively change the state of the triggers of the reversible pulse counter 3 until all of them are set to the logical zero state. In this case, at the output less than zero of the reversible pulse counter 3, a pulse occurs, which sets the RS flip-flop 4 to such a state that its output, connected to the input of the And 2 element, causes a logical Zero state and further arrival of the pulses to the subtracting input the reversing pulse counter 3 through the AND 2 is terminated. Simultaneously with this, another RS RSFighter 4 sets the state of the logical unit, which through the element OR 9 enters the recording input of the reversible pulse counter 3, the information (number A) is recorded from the input data bus 10. With the arrival of a pulse from the output generator 5 with the following frequency f RS-flip-flop 4 is set to a state in which the element 2 is reopened, the setting of the number A on the reversible pulse counter 3 is prohibited, since the logical voltage is applied to its recording input through the element OR 9 l with RS-flip-flop 4. Thus, at the output of the element And 2 we get a pack with the number of pulses equal to the set number A at intervals determined by the frequency fj from generator 5.

If the control action from the output of the control unit 6 corresponds to a logical zero, the element And 2 is closed, and the control signal, inverted by inverter 7, is fed to the input of the element And 8 and the pulses from the output of the generator 1 are fed to the summing input of the reversible pulse counter 3. The impulse from the overflow output of the reversing pulse counter 3, passing through the OR 9 element to the recording input, allows the installation of the code of the number A from the input data bus 10. At the overflow output of the reversing counter of pulses 3, we get an hour This is the pulse following fj f, / A.

Thus, when switching operating modes, the input signal f is then applied to the summing, then to the subtracting inputs of the reversible pulse counter 3, resulting in the following: a pulse sequence with the number of pulses in the packet corresponding to the written number A - on one The output of the device is a pulse, the duration of which is equal to the duration of the pulse sequence of the first output, at the other house of the RS flip-flop, the direct output of which is impulses.

connected to the first input of the second element AND, the output of the OR element is connected to the recording input of the reversible pulse counter, the summing input of which is connected to the output of the first element AND, and the subtracting input to the output of the second element AND whose second input is connected to the output of the control unit, the output of the first gene The rator is connected to the third input of the second element I and the first input of the first element I, the second input of which is connected via an inverter to the output of the control unit.

Claims (1)

Invention Formula A pulse sequence generator containing a first generator, an element, and a second generator, the output of which is connected to the installation input of an RS flip-flop, whose preset input is connected to the output is less than a zero pulse counter, whose information inputs are connected to an input data bus, characterized in that In order to expand the functional possibilities, a control unit, an inverter, a second AND element, an OR element, whose first input is connected to the overflow output of a reversible counter, are entered into it. mpulsov and a second input coupled to an inverted output RS-flip-flop, a direct output koto- RS-trigger house, direct output connected to the first input of the second element AND, the output of the OR element is connected to the recording input of a reversible pulse counter, the summing input of which is connected to the output of the first element AND, and the subtracting input to the output of the second element AND whose second input is connected to the output of the control unit, the output of the first generator connected to the third input of the second element I and the first input of the first element I, the second input of which through the inverter is connected to the output of the control unit.