SU1480101A1 - Flip-flop - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation systems, as well as in nodes of digital computing. The purpose of the invention is simplification. To achieve this goal, elements AND 4-7 and two elements HE 8.9 with an increased delay are introduced into the device. The device also contains RS-triggers 1,2, element 3, outputs 10-12, inputs 13, 14 and bus 15 installation. The simplification is due to the fact that instead of two keys with remembering the control signal, a simpler set of elements is introduced while maintaining the functionality. 1 tab., 2 Il.

Description

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eight

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The invention relates to a pulse technique and can be used in automation systems, as well as in the nodes of digital computing.

The aim of the invention is to simplify the trigger device by eliminating two keys with remembering the control signal and introducing a simpler combination of four AND elements, two NOT elements with increased delay, and new interconnects 0

FIG. 1 shows a functional scheme of a trigger device; in fig. 2 - time diagrams of its functioning u

The trigger device (Fig. 1) contains the first and second RS-flip-flops 1 and 2, the first-fifth elements AND 3-7, the first and second elements HE 8 and 9 with increased delay, the first-third outputs 10-12, the first and second inputs 13 and 14 and the bus 15 of the installation.

The direct outputs of the RS-flip-flops 1 and 2 are connected respectively to the outputs 10 and 11, and the inverse outputs to the inputs of the IZ element, the output of which is connected to the output 12. The bus 15 of the installation is connected to the first R-inputs of the RS-flip-flops 1 and 20 Input 13 connected to the first inputs of the And 4 and 5 elements and the input of the HE 8 element with an increased delay, the output of which is connected to the second inputs of the And 4 and 5 elements. The outputs of the latter are connected respectively to the S input of RS flip-flop 1 and the second R input of RS flip-flop 2. Input 14 is connected to the first inputs of the elements AND 6 and 7 and the input of the element NO 9 with uv personal delay, the output of which is connected to the second inputs of elements 6 and 7, the outputs of the latter are connected respectively to the S input of RS flip-flop 2 and the second R input of RS flip-flop Ie Inverted outputs of RS flip-flops 1 and 2 are connected respectively to the third inputs of the elements And 5 and 4 and the third inputs of the elements And 6 and 70

The trigger device operates as follows.

The pre-trigger device is reset. For this purpose, a logical unit (high potential

Q

five

0 5

0 0

five

0

five

voltage), therefore, high potentials appear at the inverse outputs of the RS flip-flops 1 and 2, the first element 3 opens and a logical unit is set at the third output 12 of the device. At the same time, logical zeros are set at the outputs 10 and 11 of the device.

To change the state of a trigger device, logical units in a certain order are fed to the inputs 13 and 14 of the device. In this case, the simultaneous supply of logical units to both inputs 13 and 14 is an unauthorized combination

Suppose the logical unit is fed to the first input 13 of the device. After time 2 (C is the delay time of the logical elements AND 3-7; 2 Ј is the switching time of the RS flip-flops 1 and 2; 3 is the delay time of the HE elements 8 and 9 with an increased delay) the logical unit is set at the output of the second element AND 4, since at its second and third inputs there are high potentials from the outputs of the first element HE 8, respectively, with an increased delay and the inverse output of the second RS flip-flop 2 “Through time 31 after high potential is applied to the first input 13 of the trigger device at the output of the first element HE 8 s increased A low potential appears at the delay, which closes the element AND 4. As a result, at the output of the second element AND 4, an impulse of the duration of the ES, which is sufficient to switch the first RS flip-flop 1 to the unit state, is outputted. At the first output 10 of the trigger device a logical unit, and at the third output 12 - a logical zero.

Repeatedly supplying a logical unit to the first input 13 of the device does not change its state. To change the state of the device, you must submit a logical one to the second input 14 of the device. As a result, the fifth element AND 7 will open, since at its second and third inputs there are logical units respectively from the output of the second element HE 9 with an increased delay and inverse output of the second RS flip-flop 2. High potential at the output of the fifth element And 7 will exist therefore, the first RS flip-flop 1 goes into the zero state, the flip-flop device is reset, the low potential is set at the first output 10, and the high potential is set at the third output 12

To change the state of the trigger device, a logical unit is fed to the second input 14, the fourth element AND 6 is opened, because its inputs contain logical units from the inverse output of the first RS flip-flop 1 and the second HE element 9 with an increased delay. As a result, a high potential will exist at the output of the fourth element And 6 over a period of 3 €, which puts the second RS-flip-flop 2 into one state, therefore, a logical one is set at the second output 11 of the flip-flop device, and a logical zero at the third output 12 Repeatedly supplying the logical unit to the second input 14 of the trigger device does not change its status. To reset the trigger device, it is necessary to apply the logical unit to the first input 13 and t "d"

The operation of the trigger device is illustrated in a timing diagram, which is shown in FIG. 2 "The timing diagram shows the output states of all logic elements, inputs 13, 14 and 15 of the device and its outputs 10, 11 and 12, as well as the states of the inverse outputs of RS flip-flops 1 and 2. The timing diagram takes into account that switching one arm the trigger is ahead of the switching of the second arm by the time Ј. The duration of the input signals must be at least 3 С, therefore, on the time diagram, the duration of the input signals is 4 С „

The table shows the state of the trigger device.

In the table, Q, Q, Q, and Q3 correspond to the states of the first 10, second 11, and third 12 outputs of the trigger device. The characteristic equations for Q ,,, Q and Q e are:

  (G4) -d4, o. (13) (

Q Г С) Q Xi v (ГЗ) - (Г4) - (tf;

QV

(lavoo-QVhVjViab

414)) -04 Q.

Claims (1)

5 claims o five 0 five 0 five 0 five A trigger device containing two inputs, an installation bus, two RS-flip-flops and the first AND element, direct outputs of the first and second RS-flip-flops are connected respectively to the first and second outputs, the inverse outputs of the RS-flip-flops are connected to the inputs of the first And element, the output of which connected to the third output, the installation bus is connected to the first R inputs of the RS flip-flops, characterized in that, for the purpose of simplification, the second, third, fourth and fifth elements AND and two elements are NOT with an increased delay, the first input is connected from the first entrance and the second and third elements And the input of the first element is NOT with an increased delay, the output of which is connected to the second inputs of the second and third elements And, the outputs of which are connected respectively to the S input of the first and second R input of the second RS trigger, the second input connected to the first inputs of the fourth and fifth elements AND and the input of the second element NOT with an increased delay, the output of which is connected to the second inputs of the fourth and fifth elements AND, the outputs of which are connected respectively to the S input of the second and second R input of the first second RS-trigger, the inverted outputs of the first and second RS-flip-flops are respectively connected to third inputs of the third and second AND gates and the third inputs of the fourth and fifth AND gates " 50 55