JPS57139852A - Parallel-serial converter - Google Patents

Parallel-serial converter

Info

Publication number
JPS57139852A
JPS57139852A JP2595581A JP2595581A JPS57139852A JP S57139852 A JPS57139852 A JP S57139852A JP 2595581 A JP2595581 A JP 2595581A JP 2595581 A JP2595581 A JP 2595581A JP S57139852 A JPS57139852 A JP S57139852A
Authority
JP
Japan
Prior art keywords
selective
parallel
clock
flop
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2595581A
Other languages
Japanese (ja)
Inventor
Hidetsugu Komiya
Michiya Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Fujitsu Fanuc Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp, Fujitsu Fanuc Ltd filed Critical Fanuc Corp
Priority to JP2595581A priority Critical patent/JPS57139852A/en
Publication of JPS57139852A publication Critical patent/JPS57139852A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Communication Control (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To execute parallel-serial conversion of optional bit length, and to economically repair a device when it is faulty, by providing a parallel-serial converting unit element of 1 bit share in accordance with each parallel output bit, and constituting the titled device in cascade connection. CONSTITUTION:When a clock pulse (cp) and a selective strobe pulse (sp) are applied simultaneously to a clock signal input terminal CLIN and a selective strobe signal input terminal SBIN, an output buffer amplifier AMP is set to an active state by an AND circuit AND1, a data applied to a parallel data input terminal PDIN is sent out onto a data line ld. Also, the clock puse (cp) is applied to a clock terminal C of a flip-flop FF1, too, therefore, the selective strobe signal is set to the flip-flop FF1, its output Q is set to ''1'', and the flip-flop FF1 delays the selective strobe pulse (sp) by 1 clock period, and sends it out to a selective strobe signal output terminal SBOUT.
JP2595581A 1981-02-24 1981-02-24 Parallel-serial converter Pending JPS57139852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2595581A JPS57139852A (en) 1981-02-24 1981-02-24 Parallel-serial converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2595581A JPS57139852A (en) 1981-02-24 1981-02-24 Parallel-serial converter

Publications (1)

Publication Number Publication Date
JPS57139852A true JPS57139852A (en) 1982-08-30

Family

ID=12180173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2595581A Pending JPS57139852A (en) 1981-02-24 1981-02-24 Parallel-serial converter

Country Status (1)

Country Link
JP (1) JPS57139852A (en)

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