SU1487167A1 - Digital pulse-width modulator - Google Patents

Description

The invention relates to a pulse technique and can be used in systems for transmitting and converting information, as well as in automatic control systems. The purpose of the invention is to increase

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information transfer rates - achieved by normalizing the pause between adjacent pulse-width signals. For this purpose, pulse-modulator 6 and functional 5 blocks and the second element OR 7 are additionally introduced into the pulse-width modulator. The modulator also contains trigger 1, counter 2 pulses, AND-NE element 3, element OR 4. Pulse unit 6 converts a high level of the functional output of the resolution block in a pulse of a given duration, which is determined by the time required to record information in the counter and install the trigger. Compared with the prototype, the speed of information transfer is doubled. 1 il.

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The invention relates to a pulse technique and can be used in systems for transmitting and converting information, as well as in automatic control systems.

The purpose of the invention is to increase the speed of information transfer due to the normalization of the pause between adjacent pulse-width signals.

The drawing shows the functional diagram of the digital pulse-width modulator.

The proposed modulator contains a trigger 1, a pulse counter 2, the element AND-NOT 3, the element OR 4, the functional unit 5, the pulse unit 6, the element OR 7, while the outputs of the trigger 1 are connected to the output buses, K-input - with the output of the element OR 4 and the first input of the element OR 7. To-input - with the output of the pulse unit 6 and the input of the recording resolution of the pulse counter 2, the overflow output of which is connected to the L-input of the trigger 1 and the second input of the element OR 7, and the information inputs to the information outputs of the functional block 5, the inputs of the element 4 OR in rows AND-NO element 3, whose output is connected to the input of flip-flop 8 1 and the third input of the OR gate 7 whose output is connected to the adjusting input of the function block 5, which permits the output connected to the input pulse unit 6.

Functional block 5 can be implemented in various ways, for example, based on a K 580 microprocessor and must necessarily contain the following components: a microprocessor, memory (RAM and ROM), input-output means (input and output ports), a synchronization generator and a power supply. It should perform the following functions: according to the signal at its installation input, prepare information at its information outputs, then set the appropriate signal at the resolution output and go on waiting for the next signal at its installation input.

Preparation of information can be done programmatically.

From an infinite loop, the microprocessor should output special commands from peripheral devices after loading the required information into RAM.

The operation of the functional unit can be controlled through the lines ΚΕΑΟΥ and У7А1Т of the microprocessor. The output of the resolution of the functional unit is connected to the AUCT line of the microprocessor. A high level appears on it after the НТТ command, when the processor has set the corresponding value on the information outputs of the function block and has switched to the standby mode. The installation input of the function block is the input

ΚΕΑϋΥ microprocessor, when a high level appears at which the program starts with a zero address.

Pulse unit 6 must convert a high level of the output of the resolution of the functional unit into a pulse of a given duration, which is determined by the time required to write information to the counter and. trigger setup. It can be implemented, for example, on the inverter, the elements of coincidence and delay, and the output of the element of coincidence is connected to the output of the pulse unit and through a series-connected inverter and delay element to the first input of the element of coincidence, the second input of which is connected to the input of the pulse unit 6. Delay element can be implemented on series-connected elements of coincidence or inverters.

Digital pulse-width modulator operates as follows.

First, information is entered into the functional block 5, then a signal is sent via the ΚΕΑΩΥ line.

Function block 5 (microprocessor) determines the current bit and sets a certain value of information outputs. After that, it issues a signal at its resolution output, which is converted by the pulse unit 6 to a pulse of a certain duration, which sets the trigger 1 and writes information to the counter 2. After that, the counter state changes (the sync bus is not shown in the drawing). After the overflow of counter 2, a signal is issued to reset trigger 1. If the code consists of all “O” or “1”, then the trigger is controlled by signals from the inputs K and 5, respectively, of the elements OR 4 or IS-NOT 3, turning into a uniquely specified state. Any of the signals from the outputs of the elements OR 4, or AND-NOT 3, or the output of the overflow ”of the counter affects the line цес of the microprocessor through the element OR 7, after which the process repeats until all are selected, for example, 65258, the information bits, after which the processor goes into standby mode without setting the signal ΨΑΙΤ (infinite loop).

Thus, the formation of the next PWM signal begins after a specified time interval (program operation) after the end of the previous one. This interval can be regulated by the introduction of commands ΝϋΡ (which do not produce actions, but consume processor time) or counting cycles. As a result, an increase in the information transmission rate is achieved, since the transmission cycle time is minimal each time and is equal to the sum of the PWM signal times and the specified interval.

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The gain in speed can be estimated as follows. Let τ be the time of a given interval, T be the time of the maximum PWM signal and a known modulator. Then, neglecting τ compared to T, we have the cycle time of information transfer:

T _h = T + t “T.

Since the time of maximum PWMsignal T, and the minimum - 0, the average time Tc _P PWM signal

t, _p = W = t

which is equal to the average transfer cycle of the proposed modulator.

Thus, in comparison with the known modulator, an increase in the speed of information transfer is ensured by 2 times.

Claims (1)

Claim Digital pulse width modulator containing a trigger, the outputs of which 6 connected to the output tires of the device, K-input - with the output of the first element OR, L-input - with the output of the pulse counter overflow, the counting input of which is connected to the bus of clock pulses, and the information inputs - with the inputs of the first element OR and the inputs of the AND-NOT element The output of which is connected to the 8-inlet.trigger, characterized in that, in order to increase the speed of information transfer, it additionally introduces a pulsed and functional blocks and a second OR element, whose inputs are connected to the Κ-, I- and 5-inputs of the trigger and the exit is with a set The main input of the functional unit, the information outputs of which are connected to the inputs of the NAND element, and the resolution output via the pulse unit - to the K-input of the trigger and the resolution input to record the information of the pulse counter.