JPS57130463A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS57130463A
JPS57130463A JP56016651A JP1665181A JPS57130463A JP S57130463 A JPS57130463 A JP S57130463A JP 56016651 A JP56016651 A JP 56016651A JP 1665181 A JP1665181 A JP 1665181A JP S57130463 A JPS57130463 A JP S57130463A
Authority
JP
Japan
Prior art keywords
gate
thickness
speed
arithmetical
fets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56016651A
Other languages
English (en)
Inventor
Fujio Masuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56016651A priority Critical patent/JPS57130463A/ja
Priority to US06/344,047 priority patent/US4525811A/en
Publication of JPS57130463A publication Critical patent/JPS57130463A/ja
Priority to US06/723,294 priority patent/US4627153A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
JP56016651A 1981-02-06 1981-02-06 Semiconductor memory Pending JPS57130463A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP56016651A JPS57130463A (en) 1981-02-06 1981-02-06 Semiconductor memory
US06/344,047 US4525811A (en) 1981-02-06 1982-01-29 Semiconductor memory and method of producing the same
US06/723,294 US4627153A (en) 1981-02-06 1985-04-15 Method of producing a semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56016651A JPS57130463A (en) 1981-02-06 1981-02-06 Semiconductor memory

Publications (1)

Publication Number Publication Date
JPS57130463A true JPS57130463A (en) 1982-08-12

Family

ID=11922243

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56016651A Pending JPS57130463A (en) 1981-02-06 1981-02-06 Semiconductor memory

Country Status (2)

Country Link
US (2) US4525811A (ja)
JP (1) JPS57130463A (ja)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4675982A (en) * 1985-10-31 1987-06-30 International Business Machines Corporation Method of making self-aligned recessed oxide isolation regions
US4951112A (en) * 1987-01-28 1990-08-21 Advanced Micro Devices, Inc. Triple-poly 4T static ram cell with two independent transistor gates
JP2509706B2 (ja) * 1989-08-18 1996-06-26 株式会社東芝 マスクｒｏｍの製造方法
KR100199258B1 (ko) * 1990-02-09 1999-06-15 가나이 쓰도무 반도체집적회로장치
US5057449A (en) * 1990-03-26 1991-10-15 Micron Technology, Inc. Process for creating two thicknesses of gate oxide within a dynamic random access memory
US5327002A (en) * 1991-05-15 1994-07-05 Kawasaki Steel Corporation SRAM with gate oxide films of varied thickness
TW208088B (ja) * 1991-05-16 1993-06-21 American Telephone & Telegraph
US5485019A (en) 1992-02-05 1996-01-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US5342798A (en) * 1993-11-23 1994-08-30 Vlsi Technology, Inc. Method for selective salicidation of source/drain regions of a transistor
US5570312A (en) * 1994-03-21 1996-10-29 United Microelectronics Corporation SRAM cell using word line controlled pull-up NMOS transistors
KR0136935B1 (ko) * 1994-04-21 1998-04-24 문정환 메모리 소자의 제조방법
JP3290827B2 (ja) * 1994-09-01 2002-06-10 東芝マイクロエレクトロニクス株式会社 半導体装置とその製造方法
JPH08111462A (ja) * 1994-10-12 1996-04-30 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
US5703392A (en) * 1995-06-02 1997-12-30 Utron Technology Inc Minimum size integrated circuit static memory cell
JP4198201B2 (ja) * 1995-06-02 2008-12-17 株式会社ルネサステクノロジ 半導体装置
US5863819A (en) 1995-10-25 1999-01-26 Micron Technology, Inc. Method of fabricating a DRAM access transistor with dual gate oxide technique
US5691217A (en) * 1996-01-03 1997-11-25 Micron Technology, Inc. Semiconductor processing method of forming a pair of field effect transistors having different thickness gate dielectric layers
US5926708A (en) * 1997-05-20 1999-07-20 International Business Machines Corp. Method for providing multiple gate oxide thicknesses on the same wafer
JPH10335656A (ja) * 1997-06-03 1998-12-18 Toshiba Corp 半導体装置の製造方法
US5939762A (en) * 1997-06-26 1999-08-17 Integrated Device Technology, Inc. SRAM cell using thin gate oxide pulldown transistors
JP3467416B2 (ja) * 1998-04-20 2003-11-17 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置及びその製造方法
US6009023A (en) * 1998-05-26 1999-12-28 Etron Technology, Inc. High performance DRAM structure employing multiple thickness gate oxide
US6383861B1 (en) 1999-02-18 2002-05-07 Micron Technology, Inc. Method of fabricating a dual gate dielectric
US6165918A (en) * 1999-05-06 2000-12-26 Integrated Device Technology, Inc. Method for forming gate oxides of different thicknesses
WO2002101833A1 (en) * 2001-06-07 2002-12-19 Amberwave Systems Corporation Multiple gate insulators with strained semiconductor heterostructures
US20030218218A1 (en) * 2002-05-21 2003-11-27 Samir Chaudhry SRAM cell with reduced standby leakage current and method for forming the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4183093A (en) * 1975-09-04 1980-01-08 Hitachi, Ltd. Semiconductor integrated circuit device composed of insulated gate field-effect transistor
JPS5582465A (en) * 1978-12-15 1980-06-21 Toshiba Corp Semiconductor device and its preparation
JPS5583265A (en) * 1978-12-19 1980-06-23 Fujitsu Ltd Semiconductor device and method of fabricating the same

Also Published As

Publication number Publication date
US4525811A (en) 1985-06-25
US4627153A (en) 1986-12-09

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