JPS57130156A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS57130156A
JPS57130156A JP56014325A JP1432581A JPS57130156A JP S57130156 A JPS57130156 A JP S57130156A JP 56014325 A JP56014325 A JP 56014325A JP 1432581 A JP1432581 A JP 1432581A JP S57130156 A JPS57130156 A JP S57130156A
Authority
JP
Japan
Prior art keywords
latch
circuit
group
timing
combinatorial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56014325A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6261973B2 (enrdf_load_stackoverflow
Inventor
Toshio Igarashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56014325A priority Critical patent/JPS57130156A/ja
Publication of JPS57130156A publication Critical patent/JPS57130156A/ja
Publication of JPS6261973B2 publication Critical patent/JPS6261973B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318577—AC testing, e.g. current testing, burn-in
    • G01R31/31858—Delay testing

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP56014325A 1981-02-04 1981-02-04 Integrated circuit Granted JPS57130156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56014325A JPS57130156A (en) 1981-02-04 1981-02-04 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56014325A JPS57130156A (en) 1981-02-04 1981-02-04 Integrated circuit

Publications (2)

Publication Number Publication Date
JPS57130156A true JPS57130156A (en) 1982-08-12
JPS6261973B2 JPS6261973B2 (enrdf_load_stackoverflow) 1987-12-24

Family

ID=11857915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56014325A Granted JPS57130156A (en) 1981-02-04 1981-02-04 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS57130156A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63279180A (ja) * 1987-05-12 1988-11-16 Nec Corp 論理回路試験機

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63279180A (ja) * 1987-05-12 1988-11-16 Nec Corp 論理回路試験機

Also Published As

Publication number Publication date
JPS6261973B2 (enrdf_load_stackoverflow) 1987-12-24

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