JPS57114243A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS57114243A JPS57114243A JP56000439A JP43981A JPS57114243A JP S57114243 A JPS57114243 A JP S57114243A JP 56000439 A JP56000439 A JP 56000439A JP 43981 A JP43981 A JP 43981A JP S57114243 A JPS57114243 A JP S57114243A
- Authority
- JP
- Japan
- Prior art keywords
- mounting section
- package
- semiconductor device
- ceramic package
- cost
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/48091—Arched
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/484—Connecting portions
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- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
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- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H01L2224/838—Bonding techniques
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- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/85424—Aluminium (Al) as principal constituent
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H01L2924/01013—Aluminum [Al]
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- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
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- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
PURPOSE:To enable to perform a microscopic work on the package wiring as well as to cut down the cost of the subject semiconductor device by a method wherein the wiring layer and the mounting section of a ceramic package are constituted chiefly of Al, and an Al eutectic alloy metal is used for the pellet adhering layer of the mounting section. CONSTITUTION:The wiring layer 7, consisting of the material having Al as a main component, and the mounting section 8 are formed on the ceramic package 1. A thin Au foil and an IC chip 9 are placed on the mounting section 8, they are fixed on the package 1 through the intermediary of an Au-Si-Al eutectic material 10. Through these procedures, a microscopic work can be performed on the ceramic package, and the quantity of gold used can be reduced, thereby enabling to cut down the cost of the subject semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56000439A JPS57114243A (en) | 1981-01-07 | 1981-01-07 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56000439A JPS57114243A (en) | 1981-01-07 | 1981-01-07 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57114243A true JPS57114243A (en) | 1982-07-16 |
JPH0245333B2 JPH0245333B2 (en) | 1990-10-09 |
Family
ID=11473836
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56000439A Granted JPS57114243A (en) | 1981-01-07 | 1981-01-07 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57114243A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS527117A (en) * | 1975-07-08 | 1977-01-20 | Hiroshi Inoue | Method of body construction of multistory concrete building |
JPS5233480A (en) * | 1975-09-10 | 1977-03-14 | Nec Corp | Semiconductor device |
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1981
- 1981-01-07 JP JP56000439A patent/JPS57114243A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS527117A (en) * | 1975-07-08 | 1977-01-20 | Hiroshi Inoue | Method of body construction of multistory concrete building |
JPS5233480A (en) * | 1975-09-10 | 1977-03-14 | Nec Corp | Semiconductor device |
Also Published As
Publication number | Publication date |
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JPH0245333B2 (en) | 1990-10-09 |
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