JPS5694753A - Correction method of semiconductor ic chip mounted substrate - Google Patents

Correction method of semiconductor ic chip mounted substrate

Info

Publication number
JPS5694753A
JPS5694753A JP17179879A JP17179879A JPS5694753A JP S5694753 A JPS5694753 A JP S5694753A JP 17179879 A JP17179879 A JP 17179879A JP 17179879 A JP17179879 A JP 17179879A JP S5694753 A JPS5694753 A JP S5694753A
Authority
JP
Japan
Prior art keywords
defective
bonded
mounted substrate
chip
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17179879A
Other languages
Japanese (ja)
Inventor
Koichi Oguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP17179879A priority Critical patent/JPS5694753A/en
Publication of JPS5694753A publication Critical patent/JPS5694753A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/98—Methods for disconnecting semiconductor or solid-state bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To perform a correction of a defective IC by a method wherein a wire of a defective IC chip is removed and thereupon, an effective IC chip is bonded with a bonding agent and thereafter, the IC mounted substrate and an IC chip is bonded with a wire. CONSTITUTION:A metal raceway 5 of a defective IC7 is removed and upon the above-mentioned defective IC7, a good IC9 is bonded with a bonding agent 10. And thereafter, a bonding pad of the good IC9 and a substrate 2 is bonded through a wiring 11. By performing in this way, a correction of a defective IC is performed in a comparatively short time and easily, thus, enabling a sharp reduction of a cost of an IC mounted substrate.
JP17179879A 1979-12-28 1979-12-28 Correction method of semiconductor ic chip mounted substrate Pending JPS5694753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17179879A JPS5694753A (en) 1979-12-28 1979-12-28 Correction method of semiconductor ic chip mounted substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17179879A JPS5694753A (en) 1979-12-28 1979-12-28 Correction method of semiconductor ic chip mounted substrate

Publications (1)

Publication Number Publication Date
JPS5694753A true JPS5694753A (en) 1981-07-31

Family

ID=15929890

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17179879A Pending JPS5694753A (en) 1979-12-28 1979-12-28 Correction method of semiconductor ic chip mounted substrate

Country Status (1)

Country Link
JP (1) JPS5694753A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2534440A1 (en) * 1982-10-06 1984-04-13 Sintra Alcatel Sa Method for substituting an electronic component connected to the conductive tracks of a carrier substrate.
WO1985002060A1 (en) * 1983-10-24 1985-05-09 Sintra-Alcatel, S.A. Method for substituting an electronic component connected to the conductor tracks of a carrier substrate
JPS61272993A (en) * 1985-05-28 1986-12-03 株式会社東芝 Electronic component apparatus
US4806503A (en) * 1985-10-25 1989-02-21 Sharp Kabushiki Kaisha Method for the replacement of semiconductor devices
JP2002353274A (en) * 2001-05-25 2002-12-06 Nec Kagoshima Ltd Method for repairing failure of semiconductor lsi chip

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2534440A1 (en) * 1982-10-06 1984-04-13 Sintra Alcatel Sa Method for substituting an electronic component connected to the conductive tracks of a carrier substrate.
WO1985002060A1 (en) * 1983-10-24 1985-05-09 Sintra-Alcatel, S.A. Method for substituting an electronic component connected to the conductor tracks of a carrier substrate
US4567643A (en) * 1983-10-24 1986-02-04 Sintra-Alcatel Method of replacing an electronic component connected to conducting tracks on a support substrate
JPS61272993A (en) * 1985-05-28 1986-12-03 株式会社東芝 Electronic component apparatus
JPH0379876B2 (en) * 1985-05-28 1991-12-20 Tokyo Shibaura Electric Co
US4806503A (en) * 1985-10-25 1989-02-21 Sharp Kabushiki Kaisha Method for the replacement of semiconductor devices
JP2002353274A (en) * 2001-05-25 2002-12-06 Nec Kagoshima Ltd Method for repairing failure of semiconductor lsi chip

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