JPS57111045A - Laying out method for integrated circuit cell - Google Patents

Laying out method for integrated circuit cell

Info

Publication number
JPS57111045A
JPS57111045A JP55188931A JP18893180A JPS57111045A JP S57111045 A JPS57111045 A JP S57111045A JP 55188931 A JP55188931 A JP 55188931A JP 18893180 A JP18893180 A JP 18893180A JP S57111045 A JPS57111045 A JP S57111045A
Authority
JP
Japan
Prior art keywords
integrated circuit
cells
out method
laying out
circuit cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55188931A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0145227B2 (enrdf_load_stackoverflow
Inventor
Yoshiyuki Suehiro
Shunzo Oota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55188931A priority Critical patent/JPS57111045A/ja
Publication of JPS57111045A publication Critical patent/JPS57111045A/ja
Publication of JPH0145227B2 publication Critical patent/JPH0145227B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP55188931A 1980-12-26 1980-12-26 Laying out method for integrated circuit cell Granted JPS57111045A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55188931A JPS57111045A (en) 1980-12-26 1980-12-26 Laying out method for integrated circuit cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55188931A JPS57111045A (en) 1980-12-26 1980-12-26 Laying out method for integrated circuit cell

Publications (2)

Publication Number Publication Date
JPS57111045A true JPS57111045A (en) 1982-07-10
JPH0145227B2 JPH0145227B2 (enrdf_load_stackoverflow) 1989-10-03

Family

ID=16232391

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55188931A Granted JPS57111045A (en) 1980-12-26 1980-12-26 Laying out method for integrated circuit cell

Country Status (1)

Country Link
JP (1) JPS57111045A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59145564A (ja) * 1983-02-09 1984-08-21 Matsushita Electronics Corp 半導体集積装置
JPH01161857A (ja) * 1987-12-18 1989-06-26 Toshiba Corp 半導体集積回路
US5359212A (en) * 1988-08-12 1994-10-25 Kabushiki Kaisha Toshiba Integrated circuit with layout effective for high-speed processing

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59145564A (ja) * 1983-02-09 1984-08-21 Matsushita Electronics Corp 半導体集積装置
JPH01161857A (ja) * 1987-12-18 1989-06-26 Toshiba Corp 半導体集積回路
US5359212A (en) * 1988-08-12 1994-10-25 Kabushiki Kaisha Toshiba Integrated circuit with layout effective for high-speed processing

Also Published As

Publication number Publication date
JPH0145227B2 (enrdf_load_stackoverflow) 1989-10-03

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