JPS57133662A - Master sliced large scale integration substrate - Google Patents

Master sliced large scale integration substrate

Info

Publication number
JPS57133662A
JPS57133662A JP1900281A JP1900281A JPS57133662A JP S57133662 A JPS57133662 A JP S57133662A JP 1900281 A JP1900281 A JP 1900281A JP 1900281 A JP1900281 A JP 1900281A JP S57133662 A JPS57133662 A JP S57133662A
Authority
JP
Japan
Prior art keywords
corner sections
wiring
substrate
array
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1900281A
Other languages
Japanese (ja)
Inventor
Minoru Nomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1900281A priority Critical patent/JPS57133662A/en
Publication of JPS57133662A publication Critical patent/JPS57133662A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To relieve the partial jam of wiring with the improvement of the degree of integration by removing the cells of the four corners of an array and increasing a wiring region in the LSI substrate in which the cells consisting of transistors, resistors, etc. are arranged and formed in array-shaped forms. CONSTITUTION:A cell array 21 and power supply buses 9 are disposed to the central section of a substrate 1, peripheral circuits 5 and input/output connecting wires 8 are shaped to a surrounding section, and An LSI substrate 1 according to a master slice system is constituted. A plurality of transistors 31, resistors 32, etc. mutually isolated electrically are formed to each cell 3 arranged in (n) lines and (m) rows, but the cells 3 are not disposed at the four corner sections 21a of the cell array 21, and the four corner sections are utilized as the wiring regions 10. Accordingly, the partial jam of virtual input/output terminals 7, which are connected through the peripheral circuits 5 and the connecting wires 8 from input/output terminals 4 and crowd at four corner sections on an internal and external boundary line 6, and wiring with the cell array 21 at the four corner sections can be prevented on the substrate integrated to a high degree.
JP1900281A 1981-02-13 1981-02-13 Master sliced large scale integration substrate Pending JPS57133662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1900281A JPS57133662A (en) 1981-02-13 1981-02-13 Master sliced large scale integration substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1900281A JPS57133662A (en) 1981-02-13 1981-02-13 Master sliced large scale integration substrate

Publications (1)

Publication Number Publication Date
JPS57133662A true JPS57133662A (en) 1982-08-18

Family

ID=11987322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1900281A Pending JPS57133662A (en) 1981-02-13 1981-02-13 Master sliced large scale integration substrate

Country Status (1)

Country Link
JP (1) JPS57133662A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601859A (en) * 1983-06-17 1985-01-08 Fujitsu Ltd Resin-sealed semiconductor device
US4593205A (en) * 1983-07-01 1986-06-03 Motorola, Inc. Macrocell array having an on-chip clock generator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601859A (en) * 1983-06-17 1985-01-08 Fujitsu Ltd Resin-sealed semiconductor device
US4593205A (en) * 1983-07-01 1986-06-03 Motorola, Inc. Macrocell array having an on-chip clock generator

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