JPS57106255A - Bit synchronizing system - Google Patents
Bit synchronizing systemInfo
- Publication number
- JPS57106255A JPS57106255A JP55182620A JP18262080A JPS57106255A JP S57106255 A JPS57106255 A JP S57106255A JP 55182620 A JP55182620 A JP 55182620A JP 18262080 A JP18262080 A JP 18262080A JP S57106255 A JPS57106255 A JP S57106255A
- Authority
- JP
- Japan
- Prior art keywords
- mpu3
- clock
- acquisition
- frequency divider
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55182620A JPS57106255A (en) | 1980-12-23 | 1980-12-23 | Bit synchronizing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55182620A JPS57106255A (en) | 1980-12-23 | 1980-12-23 | Bit synchronizing system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57106255A true JPS57106255A (en) | 1982-07-02 |
JPH0157539B2 JPH0157539B2 (ja) | 1989-12-06 |
Family
ID=16121466
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55182620A Granted JPS57106255A (en) | 1980-12-23 | 1980-12-23 | Bit synchronizing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57106255A (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6163127A (ja) * | 1984-09-04 | 1986-04-01 | Fujitsu Ltd | 時分割多重変換装置 |
JPS63156449A (ja) * | 1986-12-19 | 1988-06-29 | Sanyo Electric Co Ltd | クロツク信号再生回路 |
JPS63199537A (ja) * | 1986-12-15 | 1988-08-18 | マイテル・コーポレーション | クロック信号同期装置 |
JPH07183881A (ja) * | 1993-12-22 | 1995-07-21 | Daiden Co Ltd | クロック再生装置 |
JP2008187071A (ja) * | 2007-01-31 | 2008-08-14 | Nippon Seiki Co Ltd | プリント基板 |
-
1980
- 1980-12-23 JP JP55182620A patent/JPS57106255A/ja active Granted
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6163127A (ja) * | 1984-09-04 | 1986-04-01 | Fujitsu Ltd | 時分割多重変換装置 |
JPH0356493B2 (ja) * | 1984-09-04 | 1991-08-28 | ||
JPS63199537A (ja) * | 1986-12-15 | 1988-08-18 | マイテル・コーポレーション | クロック信号同期装置 |
JPS63156449A (ja) * | 1986-12-19 | 1988-06-29 | Sanyo Electric Co Ltd | クロツク信号再生回路 |
JPH07183881A (ja) * | 1993-12-22 | 1995-07-21 | Daiden Co Ltd | クロック再生装置 |
JP2008187071A (ja) * | 2007-01-31 | 2008-08-14 | Nippon Seiki Co Ltd | プリント基板 |
Also Published As
Publication number | Publication date |
---|---|
JPH0157539B2 (ja) | 1989-12-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5720052A (en) | Input data synchronizing circuit | |
CA2102406A1 (en) | Apparatus for and Method of Synchronizing a Clock Signal | |
JPS57106255A (en) | Bit synchronizing system | |
JPS5797251A (en) | High speed phase lock system for digital phase locking circuit | |
US4169246A (en) | Digital carrier correction circuit | |
JPS5686582A (en) | Quantizing system at reception side for video information transmitter | |
GB1444409A (en) | Pulse amplitude modulated data receiver | |
TW200723695A (en) | Phase error determination method and digital phase-locked loop system | |
GB2191068A (en) | Electrical apparatus for extracting clock signals | |
JPS56160175A (en) | Synchronous signal generator | |
JPS5651176A (en) | Signal processor | |
JPS5748841A (en) | Clock selection system | |
JPS57131144A (en) | Clock reproducing circuit | |
JPS57107688A (en) | Sampling pulse correcting system | |
JPS566568A (en) | Sampling method for facsimile signal | |
EP0200274A3 (en) | Method and circuit for the phase synchronization of a regenerated reception pulse | |
SU832758A1 (ru) | Устройство тактовой синхрониза-ции | |
JPS5431260A (en) | Digital control phase synchronizing device | |
GB1521029A (en) | Synchronous digital systems | |
SU651446A2 (ru) | Дисретный синхронизатор | |
JPS6436117A (en) | Variable delay circuit | |
SU536611A2 (ru) | Устройство синхронизации сигналов | |
JPS5715547A (en) | Data receiver | |
JPS5448473A (en) | Coder | |
JPS5624828A (en) | Phase synchronizing circuit of magnetic recorder |