JPS5624828A - Phase synchronizing circuit of magnetic recorder - Google Patents

Phase synchronizing circuit of magnetic recorder

Info

Publication number
JPS5624828A
JPS5624828A JP10008579A JP10008579A JPS5624828A JP S5624828 A JPS5624828 A JP S5624828A JP 10008579 A JP10008579 A JP 10008579A JP 10008579 A JP10008579 A JP 10008579A JP S5624828 A JPS5624828 A JP S5624828A
Authority
JP
Japan
Prior art keywords
phase
circuit
input
output
difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10008579A
Other languages
Japanese (ja)
Inventor
Michitaka Kawada
Toshiki Okubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10008579A priority Critical patent/JPS5624828A/en
Publication of JPS5624828A publication Critical patent/JPS5624828A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To prevent the occurrence of an error due to information shift by detecting synchronism occurring although the interval between read information and a sampling pulse is less than a fixed value and then by correcting the interval. CONSTITUTION:Read information A and sampling pulse B of voltage control oscillation part 12 are input to phase-difference detecting circuit 13 to detect a phase difference between both the signals and its output is input to low-pass filtration circuit 14. Further, phase-difference detecting circuit 16 detects the phase difference below a fixed value and generates a correction signal. The output of low-pass filter 14 and that of phase-difference detecting circuit 16 are input to level shifting circuit 15 and the oscillation frequency of voltage control oscillator 12 is controlled by the output of level shifting circuit 15.
JP10008579A 1979-08-06 1979-08-06 Phase synchronizing circuit of magnetic recorder Pending JPS5624828A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10008579A JPS5624828A (en) 1979-08-06 1979-08-06 Phase synchronizing circuit of magnetic recorder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10008579A JPS5624828A (en) 1979-08-06 1979-08-06 Phase synchronizing circuit of magnetic recorder

Publications (1)

Publication Number Publication Date
JPS5624828A true JPS5624828A (en) 1981-03-10

Family

ID=14264587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10008579A Pending JPS5624828A (en) 1979-08-06 1979-08-06 Phase synchronizing circuit of magnetic recorder

Country Status (1)

Country Link
JP (1) JPS5624828A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5107227A (en) * 1988-02-08 1992-04-21 Magellan Corporation (Australia) Pty. Ltd. Integratable phase-locked loop

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5107227A (en) * 1988-02-08 1992-04-21 Magellan Corporation (Australia) Pty. Ltd. Integratable phase-locked loop

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