JPS57104239A - Forming method for insulating layer - Google Patents

Forming method for insulating layer

Info

Publication number
JPS57104239A
JPS57104239A JP18050580A JP18050580A JPS57104239A JP S57104239 A JPS57104239 A JP S57104239A JP 18050580 A JP18050580 A JP 18050580A JP 18050580 A JP18050580 A JP 18050580A JP S57104239 A JPS57104239 A JP S57104239A
Authority
JP
Japan
Prior art keywords
substrate
layer
dosage
oxygen
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18050580A
Other languages
Japanese (ja)
Inventor
Masahiro Akitani
Sadao Nakajima
Kuniki Owada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP18050580A priority Critical patent/JPS57104239A/en
Publication of JPS57104239A publication Critical patent/JPS57104239A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To obtain an insulating substrate, which has small voltage dependency and high dielectric resistance, by controlling the rate of dosage of oxygen to predetermined value and forming and putting a mixed layer of poly Si and an SiO2 layer when oxygen ions are injected into a Si substrate and an insulator is shaped. CONSTITUTION:When oxygen ions are implanted into the Si substrate, the mixed layer 5 of poly Si and SiO2 is put between a surface Si layer 1 and an SiO2 layer 2 by controlling the rate of dosage of oxygen to 12-17.5muA/cm<2>, acceleration energy to 120kV or higher and the quantity of dosage to 1.8X10<18>cm<-2> or higher. Accordingly, the voltage dependency of the insulating separation substrate is small, its leakage currents are minimized, and this method is useful for high dielectric resistance and complementing.
JP18050580A 1980-12-22 1980-12-22 Forming method for insulating layer Pending JPS57104239A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18050580A JPS57104239A (en) 1980-12-22 1980-12-22 Forming method for insulating layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18050580A JPS57104239A (en) 1980-12-22 1980-12-22 Forming method for insulating layer

Publications (1)

Publication Number Publication Date
JPS57104239A true JPS57104239A (en) 1982-06-29

Family

ID=16084408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18050580A Pending JPS57104239A (en) 1980-12-22 1980-12-22 Forming method for insulating layer

Country Status (1)

Country Link
JP (1) JPS57104239A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6080279A (en) * 1983-10-08 1985-05-08 Nippon Telegr & Teleph Corp <Ntt> Insulated gate type transistor
US5441899A (en) * 1992-02-18 1995-08-15 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing substrate having semiconductor on insulator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5227285A (en) * 1975-08-26 1977-03-01 Sony Corp Semiconductor device
JPS52149076A (en) * 1976-06-04 1977-12-10 Hitachi Ltd Semiconductor integrated circuit and its preparing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5227285A (en) * 1975-08-26 1977-03-01 Sony Corp Semiconductor device
JPS52149076A (en) * 1976-06-04 1977-12-10 Hitachi Ltd Semiconductor integrated circuit and its preparing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6080279A (en) * 1983-10-08 1985-05-08 Nippon Telegr & Teleph Corp <Ntt> Insulated gate type transistor
US5441899A (en) * 1992-02-18 1995-08-15 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing substrate having semiconductor on insulator
US5616507A (en) * 1992-02-18 1997-04-01 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing substrate having semiconductor on insulator

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