JPS5694644A - Semiconductor ic device - Google Patents

Semiconductor ic device

Info

Publication number
JPS5694644A
JPS5694644A JP16933779A JP16933779A JPS5694644A JP S5694644 A JPS5694644 A JP S5694644A JP 16933779 A JP16933779 A JP 16933779A JP 16933779 A JP16933779 A JP 16933779A JP S5694644 A JPS5694644 A JP S5694644A
Authority
JP
Japan
Prior art keywords
blocks
supply
constitution
supply wires
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16933779A
Other languages
Japanese (ja)
Inventor
Masao Kato
Akira Masaki
Koji Masuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16933779A priority Critical patent/JPS5694644A/en
Publication of JPS5694644A publication Critical patent/JPS5694644A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain complicated LSI by arranging circuit elements in lines within nearly-rectangular blocks inside a semiconductor chip and by connecting blocks with each other through untilization of the technology of multilayer wiring constituted by supply wires in the direction of lines and those in the direction perpendicular to the former. CONSTITUTION:The rectangular blocks 10 having many gates are located on the chip 11, while supply wires 8 and 9 are laid longitudinally and laterally around the blocks. Within each block 10, supply wires 13 are arranged along each cell line 13 and connected with the supply wire 8, making the blocks equal in potential. The supply wires 9 and 13 are formed in X-directional wiring with the 1st wiring layer on the chip, while the supply wire 8 is formed in a multilayer wiring structure on the 1st wiring layer. The cell lines 12 comprise many cells 17, while the supply wire 13 is connected 15 with the diffusion layer of the cell 17, and the gate of a transistor is connected thereto with a gate wire 18. The wirings are arranged further in multilayer construction as occasion calls. By this constitution, feeding current suitable to the block constitution is conducted and thus LSI having complicated circuit constituion can be obtained.
JP16933779A 1979-12-27 1979-12-27 Semiconductor ic device Pending JPS5694644A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16933779A JPS5694644A (en) 1979-12-27 1979-12-27 Semiconductor ic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16933779A JPS5694644A (en) 1979-12-27 1979-12-27 Semiconductor ic device

Publications (1)

Publication Number Publication Date
JPS5694644A true JPS5694644A (en) 1981-07-31

Family

ID=15884679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16933779A Pending JPS5694644A (en) 1979-12-27 1979-12-27 Semiconductor ic device

Country Status (1)

Country Link
JP (1) JPS5694644A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0360507A2 (en) * 1988-09-19 1990-03-28 Fujitsu Limited Semiconductor integrated circuit device having an improved arrangement of power source lines
JPH0389536A (en) * 1989-08-31 1991-04-15 Fujitsu Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0360507A2 (en) * 1988-09-19 1990-03-28 Fujitsu Limited Semiconductor integrated circuit device having an improved arrangement of power source lines
JPH0389536A (en) * 1989-08-31 1991-04-15 Fujitsu Ltd Semiconductor device

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