JPS5688337A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS5688337A
JPS5688337A JP16653379A JP16653379A JPS5688337A JP S5688337 A JPS5688337 A JP S5688337A JP 16653379 A JP16653379 A JP 16653379A JP 16653379 A JP16653379 A JP 16653379A JP S5688337 A JPS5688337 A JP S5688337A
Authority
JP
Japan
Prior art keywords
layer
substrate
type
shielding layer
type layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16653379A
Other languages
Japanese (ja)
Inventor
Takashi Matsumoto
Kunihiko Wada
Tsutomu Ogawa
Nobuo Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16653379A priority Critical patent/JPS5688337A/en
Publication of JPS5688337A publication Critical patent/JPS5688337A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To remarkably decrease the grounding resistance of a field shielding layer formed through an insulating layer in a substrate having a P type layer on an N type layer by forming the field shielding layer in the substrate and forming an N type layer insulated from the shielding layer in the inner surface of a V-shaped groove reaching from the surface of the substrate to the N type layer. CONSTITUTION:A P type layer 2 and a P<-> type layer 3 are superposed on the N<+> type Si substrate 1, windows are opened at an SiO2 film 5, are anisotropically etched, and V-shaped grooves 8 reaching the substrate 1 are formed thereat. A polysilicon pattern 16 is selectively formed on an element isolating region 4, the layer 3 is exposed, P type ions are implanted to thereby heat treat it, and the field shielding layer 6 and the N type layer 9 are formed, and the N type layer 7 is formed in the vicinity of the V-shaped groove 8. Simultaneously, an N<+> type layer 11 is formed on the layer 3 of an element forming region 10, and is covered with an SiO2 film 5'. Thereafter, a V-MOS FET is formed in the region 10. Since in this configuration the shielding layer is connected vertically to the substrate of grounding potential with extremely low grounding resistance, the potential of the shielding layer does not vary with the potential of the wiring layer formed above the shielding layer, the grounding wire of the shielding layer is not necessarily arranged on the substrate, thereby increasing the degree of freedom of designing the wire, and there can be obtained a high performance IC.
JP16653379A 1979-12-21 1979-12-21 Semiconductor integrated circuit device Pending JPS5688337A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16653379A JPS5688337A (en) 1979-12-21 1979-12-21 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16653379A JPS5688337A (en) 1979-12-21 1979-12-21 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5688337A true JPS5688337A (en) 1981-07-17

Family

ID=15833051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16653379A Pending JPS5688337A (en) 1979-12-21 1979-12-21 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5688337A (en)

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