JPS5685857A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5685857A JPS5685857A JP16154779A JP16154779A JPS5685857A JP S5685857 A JPS5685857 A JP S5685857A JP 16154779 A JP16154779 A JP 16154779A JP 16154779 A JP16154779 A JP 16154779A JP S5685857 A JPS5685857 A JP S5685857A
- Authority
- JP
- Japan
- Prior art keywords
- plane
- groove
- etching
- oblique
- boundary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000005530 etching Methods 0.000 abstract 3
- 239000010408 film Substances 0.000 abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract 1
- 239000012670 alkaline solution Substances 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 230000000717 retained effect Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 239000000243 solution Substances 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 239000010409 thin film Substances 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Weting (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
PURPOSE:To obtain a semiconductor device having small current area, a high speed operation and low power consumption by anisotropically etching a semiconductor substrate having (100) plane, perforating a V-shaped groove having oblique (111) plane surfaces, forming diffused layers thereon, thereafter removing bottom surface of the groove, and retaining the diffused layers only on the side walls. CONSTITUTION:An SiO2 film 2 is covered on an n type Si substrate 1 having a (100) plane, a window 3 is opened thereat, it is anisotropically etched with alkaline solution, and the etching is once stopped when both the oblique (111) surfaces and the horizontal (100) surface are formed in the recess 4. Subsequently, the entire surface is oxidized, an oxide film 5 having a thickness t1 is formed on the (111) surfaces, and an oxide film 6 having a thickness t2 is formed on the (100) surface, only the thin film 6 is removed with fluoric acid solution, a p type region 7 is diffused thereat, impurity is creeped around the boundary with the (111) surface, and a p type region 8 is formed at the boundary. Thereafter, anisotropic etching is again conducted, a V-shaped groove 9 is formed, and the region 8 is retained only in the side wall of the groove 9.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16154779A JPS5685857A (en) | 1979-12-14 | 1979-12-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16154779A JPS5685857A (en) | 1979-12-14 | 1979-12-14 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5685857A true JPS5685857A (en) | 1981-07-13 |
Family
ID=15737175
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16154779A Pending JPS5685857A (en) | 1979-12-14 | 1979-12-14 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5685857A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5811336A (en) * | 1994-08-31 | 1998-09-22 | Nec Corporation | Method of forming MOS transistors having gate insulators of different thicknesses |
US6780713B2 (en) | 2001-06-29 | 2004-08-24 | Atmel Germany Gmbh | Process for manufacturing a DMOS transistor |
US6806131B2 (en) | 2001-06-29 | 2004-10-19 | Atmel Germany Gmbh | Process for manufacturing a DMOS transistor |
US6878603B2 (en) | 2001-06-29 | 2005-04-12 | Atmel Germany Gmbh | Process for manufacturing a DMOS transistor |
US6933215B2 (en) | 2001-06-29 | 2005-08-23 | Atmel Germany Gmbh | Process for doping a semiconductor body |
US7064385B2 (en) | 2003-09-19 | 2006-06-20 | Atmel Germany Gmbh | DMOS-transistor with lateral dopant gradient in drift region and method of producing the same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5343483A (en) * | 1976-10-01 | 1978-04-19 | Handotai Kenkyu Shinkokai | Semiconductor device |
JPS5591879A (en) * | 1978-12-29 | 1980-07-11 | Seiko Instr & Electronics Ltd | Electrostatic induction type transistor |
-
1979
- 1979-12-14 JP JP16154779A patent/JPS5685857A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5343483A (en) * | 1976-10-01 | 1978-04-19 | Handotai Kenkyu Shinkokai | Semiconductor device |
JPS5591879A (en) * | 1978-12-29 | 1980-07-11 | Seiko Instr & Electronics Ltd | Electrostatic induction type transistor |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5811336A (en) * | 1994-08-31 | 1998-09-22 | Nec Corporation | Method of forming MOS transistors having gate insulators of different thicknesses |
US6780713B2 (en) | 2001-06-29 | 2004-08-24 | Atmel Germany Gmbh | Process for manufacturing a DMOS transistor |
US6806131B2 (en) | 2001-06-29 | 2004-10-19 | Atmel Germany Gmbh | Process for manufacturing a DMOS transistor |
US6878603B2 (en) | 2001-06-29 | 2005-04-12 | Atmel Germany Gmbh | Process for manufacturing a DMOS transistor |
US6933215B2 (en) | 2001-06-29 | 2005-08-23 | Atmel Germany Gmbh | Process for doping a semiconductor body |
US7064385B2 (en) | 2003-09-19 | 2006-06-20 | Atmel Germany Gmbh | DMOS-transistor with lateral dopant gradient in drift region and method of producing the same |
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