JPS5673362A - Testing device of memory - Google Patents
Testing device of memoryInfo
- Publication number
- JPS5673362A JPS5673362A JP15090279A JP15090279A JPS5673362A JP S5673362 A JPS5673362 A JP S5673362A JP 15090279 A JP15090279 A JP 15090279A JP 15090279 A JP15090279 A JP 15090279A JP S5673362 A JPS5673362 A JP S5673362A
- Authority
- JP
- Japan
- Prior art keywords
- output
- memory
- selector
- generator
- delayed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
PURPOSE: To enable to generate mask patterns and to improve an activity efficiency by a method wherein a plural number of memory units for a pattern generator are installed.
CONSTITUTION: An address from a pattern generator 11 is delayed 21, and an output signal of the generator 11 or the delayed output is selected through a selector 22 to perform an access to a memory unit 23. And further, through a selector 24, the output signal of the generator 11 or the delayed output is selected to perform an access to a memory unit 25. And still, an output of the memory unit 23 or an output of the unit 25 is selected through a selector 26, or both outputs are fetched to be supplied to a comparator 16 and they are compared with the read output of the memory to be tested 13, or as for a certain address, a mask is performed to disregard a test. When a discord is obtained for a comparison output, in accordance therewith, a write control unit 29 is actuated, thus, performing a write control against the memory units 23, 25.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15090279A JPS5673362A (en) | 1979-11-21 | 1979-11-21 | Testing device of memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15090279A JPS5673362A (en) | 1979-11-21 | 1979-11-21 | Testing device of memory |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5673362A true JPS5673362A (en) | 1981-06-18 |
JPS6132757B2 JPS6132757B2 (en) | 1986-07-29 |
Family
ID=15506875
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15090279A Granted JPS5673362A (en) | 1979-11-21 | 1979-11-21 | Testing device of memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5673362A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63177772U (en) * | 1987-05-08 | 1988-11-17 |
-
1979
- 1979-11-21 JP JP15090279A patent/JPS5673362A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63177772U (en) * | 1987-05-08 | 1988-11-17 |
Also Published As
Publication number | Publication date |
---|---|
JPS6132757B2 (en) | 1986-07-29 |
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