JPS5693199A - Evaluation method of memory device - Google Patents

Evaluation method of memory device

Info

Publication number
JPS5693199A
JPS5693199A JP17247979A JP17247979A JPS5693199A JP S5693199 A JPS5693199 A JP S5693199A JP 17247979 A JP17247979 A JP 17247979A JP 17247979 A JP17247979 A JP 17247979A JP S5693199 A JPS5693199 A JP S5693199A
Authority
JP
Japan
Prior art keywords
expected
memory device
decided
generator
margin curve
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17247979A
Other languages
Japanese (ja)
Inventor
Ryuichi Usami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17247979A priority Critical patent/JPS5693199A/en
Publication of JPS5693199A publication Critical patent/JPS5693199A/en
Pending legal-status Critical Current

Links

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To reduce the necessary time for evaluation to a memory device, by testing immediately an expected memory region when a margin curve is decided to a power supply voltage.
CONSTITUTION: The device is provided with the pattern generator 1; power source 5; timing generator 6; holding register 2 which stores the value with which the expected memory region is designated when the margin curve is decided; and the address converter 3 which converts the address pattern given from the generator 1 according to the designated value of the expected recording region. When the margin curve is decided, at first the expected memory region of the memory device 4 to be tested is tested.
COPYRIGHT: (C)1981,JPO&Japio
JP17247979A 1979-12-26 1979-12-26 Evaluation method of memory device Pending JPS5693199A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17247979A JPS5693199A (en) 1979-12-26 1979-12-26 Evaluation method of memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17247979A JPS5693199A (en) 1979-12-26 1979-12-26 Evaluation method of memory device

Publications (1)

Publication Number Publication Date
JPS5693199A true JPS5693199A (en) 1981-07-28

Family

ID=15942742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17247979A Pending JPS5693199A (en) 1979-12-26 1979-12-26 Evaluation method of memory device

Country Status (1)

Country Link
JP (1) JPS5693199A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62263475A (en) * 1986-05-10 1987-11-16 Agency Of Ind Science & Technol Memory testing apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62263475A (en) * 1986-05-10 1987-11-16 Agency Of Ind Science & Technol Memory testing apparatus
JP2520234B2 (en) * 1986-05-10 1996-07-31 工業技術院長 Memory test equipment

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