JPS5671950A - Manufacture of integrated semiconductor circuit - Google Patents

Manufacture of integrated semiconductor circuit

Info

Publication number
JPS5671950A
JPS5671950A JP14890379A JP14890379A JPS5671950A JP S5671950 A JPS5671950 A JP S5671950A JP 14890379 A JP14890379 A JP 14890379A JP 14890379 A JP14890379 A JP 14890379A JP S5671950 A JPS5671950 A JP S5671950A
Authority
JP
Japan
Prior art keywords
film
groove
layer
substrate
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14890379A
Other languages
Japanese (ja)
Other versions
JPS6234147B2 (en
Inventor
Yoichi Tamaoki
Hisayuki Higuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14890379A priority Critical patent/JPS5671950A/en
Publication of JPS5671950A publication Critical patent/JPS5671950A/en
Publication of JPS6234147B2 publication Critical patent/JPS6234147B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To obtain good electric insulation characteristic and fine-workability by forming a thick oxide films and a thin oxide film at the ends and the central portion respectively of an isolation range while preventing the application of a large stress to the substrate with only the end portions oxidized selectively. CONSTITUTION:An oxide film 3 is deposited on the surface of an Si substrate 1 provided with a collector burying layer 2, a window is made, and a groove 4 is cut in the substrate 1. Next, the film 3 is removed, a polycrystalline Si layer 7 with the same thickness as the groove 4 is deposited over the whole surface including the groove 4 while filling the groove 4 of the substrate with an oxide film 5 and an Si3N4 film 6 placed therebetween, only the portion of the layer 7 is changed into SiO2 film 8 through heat-treatment, and the film 8 is covered with an Si3N4 film 9. Thereafter, a resist pattern 10 is provided on a groove 4 recess, only the films 9 and 8 are left only under the pattern 10 through the etching in which the pattern 10 is used as mask, heat-treatment is made with the pattern 10 removed, an SiO2 film 11 is formed to surround the SiO2 film 8 of the surface layer portion of the layer 7 left only in the groove 4.
JP14890379A 1979-11-19 1979-11-19 Manufacture of integrated semiconductor circuit Granted JPS5671950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14890379A JPS5671950A (en) 1979-11-19 1979-11-19 Manufacture of integrated semiconductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14890379A JPS5671950A (en) 1979-11-19 1979-11-19 Manufacture of integrated semiconductor circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP9811088A Division JPS63288044A (en) 1988-04-22 1988-04-22 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5671950A true JPS5671950A (en) 1981-06-15
JPS6234147B2 JPS6234147B2 (en) 1987-07-24

Family

ID=15463240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14890379A Granted JPS5671950A (en) 1979-11-19 1979-11-19 Manufacture of integrated semiconductor circuit

Country Status (1)

Country Link
JP (1) JPS5671950A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4804641A (en) * 1985-09-30 1989-02-14 Siemens Aktiengesellschaft Method for limiting chippage when sawing a semiconductor wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4804641A (en) * 1985-09-30 1989-02-14 Siemens Aktiengesellschaft Method for limiting chippage when sawing a semiconductor wafer

Also Published As

Publication number Publication date
JPS6234147B2 (en) 1987-07-24

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