JPS567157A - Time information transfer system - Google Patents

Time information transfer system

Info

Publication number
JPS567157A
JPS567157A JP8191479A JP8191479A JPS567157A JP S567157 A JPS567157 A JP S567157A JP 8191479 A JP8191479 A JP 8191479A JP 8191479 A JP8191479 A JP 8191479A JP S567157 A JPS567157 A JP S567157A
Authority
JP
Japan
Prior art keywords
information
time
logic
check
generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8191479A
Other languages
Japanese (ja)
Inventor
Kiyotaka Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8191479A priority Critical patent/JPS567157A/en
Publication of JPS567157A publication Critical patent/JPS567157A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To prevent the extraction of the wrong time information into the time receiver, by adding the check information to the time generator and then giving the check to the justice of the time information through the time receiver and based on the time information and the check information.
CONSTITUTION: Time information generating circuit 10 in time generator 1 generates time information 100 of the standard value of real time to plural number of time receiver 2. Check information generating circuit 11 generates check information 101 based on information 100. And effective display generating circuit 12 changes effective display signal 102 to logic 1 when generator 1 is normal, and then changes signal 102 to logic 0 in case generator 1 is faulty each. Check circuit 20 in receiver 2 checks whether the contents of information 100 is correct or not based on information 100 and 101. And when the contents is correct, error signal 103 is turned to logic 1; while signal 103 is changed t logic 0 when the contents is not correct each. The logic product of logic product gate 21 changes the state of effective display signal 104 according to the state of signals 102 and 103 each. And only when both signals 102 and 103 are logic 1, information 100 is taken into input register 22.
COPYRIGHT: (C)1981,JPO&Japio
JP8191479A 1979-06-28 1979-06-28 Time information transfer system Pending JPS567157A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8191479A JPS567157A (en) 1979-06-28 1979-06-28 Time information transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8191479A JPS567157A (en) 1979-06-28 1979-06-28 Time information transfer system

Publications (1)

Publication Number Publication Date
JPS567157A true JPS567157A (en) 1981-01-24

Family

ID=13759707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8191479A Pending JPS567157A (en) 1979-06-28 1979-06-28 Time information transfer system

Country Status (1)

Country Link
JP (1) JPS567157A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4875137A (en) * 1972-01-11 1973-10-09

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4875137A (en) * 1972-01-11 1973-10-09

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