JPS5670647A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5670647A
JPS5670647A JP14791579A JP14791579A JPS5670647A JP S5670647 A JPS5670647 A JP S5670647A JP 14791579 A JP14791579 A JP 14791579A JP 14791579 A JP14791579 A JP 14791579A JP S5670647 A JPS5670647 A JP S5670647A
Authority
JP
Japan
Prior art keywords
layer
substrate
film
type
resistance element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14791579A
Other languages
Japanese (ja)
Inventor
Hiroshi Nomura
Isao Fujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP14791579A priority Critical patent/JPS5670647A/en
Publication of JPS5670647A publication Critical patent/JPS5670647A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To electrostatically shield a semiconductor device by forming a low impurity density surface layer such as a resistance element on a semiconductor substrate, coating an insulating layer on the surface of the substrate, and further forming a conductive layer grounded through the insulating layer on the surface layer of the substrate. CONSTITUTION:A resistance element such as a bipolar IC or the like is formed by forming a P type layer 4 at the time of diffusing a base into an island region 3 isolated by a P<+> type isolation region 2 with an N type epitaxial layer 3 formed on the P type Si substrate 1. A window is formed at an SiO2 film 5 coating the surface, and connecting conductors 6, 7 are formed at both ends of the layer 4. Further, an insulating film 10 is formed thereon, a metallic film 11 is formed thereon, and the film 11 is fixed to the grounding potential. Since the resistance element in the bipolar IC or the like is electrostatically shielded by the metallic film is this manner, even if a high voltage charged article is approached to the vicinity as charged with static electricity, it can prevent the variation in the characteristics due to its affect thereto.
JP14791579A 1979-11-14 1979-11-14 Semiconductor device Pending JPS5670647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14791579A JPS5670647A (en) 1979-11-14 1979-11-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14791579A JPS5670647A (en) 1979-11-14 1979-11-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5670647A true JPS5670647A (en) 1981-06-12

Family

ID=15440969

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14791579A Pending JPS5670647A (en) 1979-11-14 1979-11-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5670647A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112271171A (en) * 2017-11-13 2021-01-26 住友电气工业株式会社 Semiconductor device and amplifier assembly

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53103385A (en) * 1977-02-22 1978-09-08 Seiko Instr & Electronics Ltd Integrated circuit for watches

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53103385A (en) * 1977-02-22 1978-09-08 Seiko Instr & Electronics Ltd Integrated circuit for watches

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112271171A (en) * 2017-11-13 2021-01-26 住友电气工业株式会社 Semiconductor device and amplifier assembly

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