JPS5649538A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the sameInfo
- Publication number
- JPS5649538A JPS5649538A JP12413479A JP12413479A JPS5649538A JP S5649538 A JPS5649538 A JP S5649538A JP 12413479 A JP12413479 A JP 12413479A JP 12413479 A JP12413479 A JP 12413479A JP S5649538 A JPS5649538 A JP S5649538A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- film
- sio2
- monocrystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76281—Lateral isolation by selective oxidation of silicon
Abstract
PURPOSE:To obtain a high voltage resistant semiconductor device without including any crystal defect by a method wherein a semiconductor substrate is of a composite substrate comprising a polycrystal and a monocrystal with an SiO2 film therebetween, the monocrystal layer is separated into the form of islands by a selective oxide reaching to the SiO2 film and the insular area is used as a circuit forming portion. CONSTITUTION:On both sides of an n<-> type monocrystal substrate 1 n type impurities are deposition-diffused to form an n<+> type layer 2 constituting a buried layer in later. An Si layer is formed by vapor phase epitaxy on one of the both sides through an SiO2 film 3 formed at the same time of the deposition diffusion to give a polycrystal Si layer 4 in the presence of the layer 3. Then, thus obtained element is fixed on a sappire substrate 5 with the layer 4 thereof in contact against the surface of the substrate 5. The upper side opposing to the layer 4 is mechanically polished to reduce a thickness of the substrate 1 and an SiO2 film 6 and an Si3N4 film 7 are coated thereon. Thereafter, the film 7 is removed from the predetermined positions to form SiO2 isolation portions 8 reaching to the film 2 of the substrate 1 at the opposite side by selective oxidation, and the substrate 1 separated into the form of islands is used as a circuit forming portion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12413479A JPS5649538A (en) | 1979-09-28 | 1979-09-28 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12413479A JPS5649538A (en) | 1979-09-28 | 1979-09-28 | Semiconductor device and method of manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5649538A true JPS5649538A (en) | 1981-05-06 |
Family
ID=14877757
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12413479A Pending JPS5649538A (en) | 1979-09-28 | 1979-09-28 | Semiconductor device and method of manufacturing the same |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5649538A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01105574A (en) * | 1987-10-19 | 1989-04-24 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1979
- 1979-09-28 JP JP12413479A patent/JPS5649538A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01105574A (en) * | 1987-10-19 | 1989-04-24 | Fujitsu Ltd | Manufacture of semiconductor device |
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