JPS5648000A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5648000A
JPS5648000A JP12260279A JP12260279A JPS5648000A JP S5648000 A JPS5648000 A JP S5648000A JP 12260279 A JP12260279 A JP 12260279A JP 12260279 A JP12260279 A JP 12260279A JP S5648000 A JPS5648000 A JP S5648000A
Authority
JP
Japan
Prior art keywords
parity
data
circuit
error
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12260279A
Other languages
Japanese (ja)
Inventor
Hiroshi Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12260279A priority Critical patent/JPS5648000A/en
Publication of JPS5648000A publication Critical patent/JPS5648000A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To perform memory read operation accurately while preventing an apparent fault of a machine by preventing an error that occurs once, by making a parity check by rereading data where a parity error has occurred.
CONSTITUTION: Information data, when read out of memory device 1 by control circuit 6 via address selecting circuit 2, is temporarily stored in data register 3 and parity generating circuit 4 generates its parity on the basis of the count value of bits of the readout data. This parity is compared to that added to information of device 1 by comparing circuit 5 and when the information data is wrong, comparator 5 generates a high-level output to erase the contents of register 3 while device 6 holds circuit 2. Consequently, the information, when the parity error occurs, is reread and checked again to prevent the occurrence of a one-chance error, so that the read operation of the memory can be performed accurately.
COPYRIGHT: (C)1981,JPO&Japio
JP12260279A 1979-09-26 1979-09-26 Information processor Pending JPS5648000A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12260279A JPS5648000A (en) 1979-09-26 1979-09-26 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12260279A JPS5648000A (en) 1979-09-26 1979-09-26 Information processor

Publications (1)

Publication Number Publication Date
JPS5648000A true JPS5648000A (en) 1981-04-30

Family

ID=14839988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12260279A Pending JPS5648000A (en) 1979-09-26 1979-09-26 Information processor

Country Status (1)

Country Link
JP (1) JPS5648000A (en)

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