JPS55153197A - Error byte detecting circuit of memory unit - Google Patents

Error byte detecting circuit of memory unit

Info

Publication number
JPS55153197A
JPS55153197A JP5932079A JP5932079A JPS55153197A JP S55153197 A JPS55153197 A JP S55153197A JP 5932079 A JP5932079 A JP 5932079A JP 5932079 A JP5932079 A JP 5932079A JP S55153197 A JPS55153197 A JP S55153197A
Authority
JP
Japan
Prior art keywords
error
byte
counter
signal
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5932079A
Other languages
Japanese (ja)
Inventor
Takashi Aoki
Hisajiro Sagara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5932079A priority Critical patent/JPS55153197A/en
Publication of JPS55153197A publication Critical patent/JPS55153197A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it easy to detect an error byte position and its cause position by providing the method of indicating a byte position where a parity error is happening by testing data.
CONSTITUTION: If data read out from buffer memory 1 has an error, register error signal 5 is generated, and consequently byte counter 8 operates to decide byte error 5' at the assigned byte position while counter 8 is made to count up in case no error. When an error is found, test pattern generating circuit 7 is put into operation to write a test pattern at the byte position of read register 3 assigned by counter 8, so that parity check circuit 4 will make a decision by byte error signal 5' in sequence. When signal 5' is generated, a byte marked by register 3 is considered to has an error. When signal 5' is not generated, the read operation of memory 1 is faulty. After an error log, circuit 7 recovers and counter 8 is made to count up by one, thereby repeating the above-mentioned operation.
COPYRIGHT: (C)1980,JPO&Japio
JP5932079A 1979-05-15 1979-05-15 Error byte detecting circuit of memory unit Pending JPS55153197A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5932079A JPS55153197A (en) 1979-05-15 1979-05-15 Error byte detecting circuit of memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5932079A JPS55153197A (en) 1979-05-15 1979-05-15 Error byte detecting circuit of memory unit

Publications (1)

Publication Number Publication Date
JPS55153197A true JPS55153197A (en) 1980-11-28

Family

ID=13109942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5932079A Pending JPS55153197A (en) 1979-05-15 1979-05-15 Error byte detecting circuit of memory unit

Country Status (1)

Country Link
JP (1) JPS55153197A (en)

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