JPS5627944A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5627944A JPS5627944A JP10282679A JP10282679A JPS5627944A JP S5627944 A JPS5627944 A JP S5627944A JP 10282679 A JP10282679 A JP 10282679A JP 10282679 A JP10282679 A JP 10282679A JP S5627944 A JPS5627944 A JP S5627944A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- wiring
- etched
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To form multilayered wiring whose surface is flat by laminating the insulating layers whose etching rates are different; thereafter opening a hole, side-etching the lower layer, depositing a metal film, and forming a metal wiring by employing the lift-off method. CONSTITUTION:An oxide film 6, semiconductor layers 4 and 5 are formed on a substrate 1 on which element is formed. Then, an SiO2 film 7, a metal 8, and a nitride film 9 are formed, and a hole is opened by the photoetching. At this time, the nitride film 9 and the SiO2 film 7 are vertically etched by the sputter etching, and the metal film 8 is side-etched in liquid. Then Al is evaporated in a vacuum, the metal film 8 is etched out, unnecessary Al is lifted off, and an Al electrode 11 is formed. The same process is repeated and the multilayered wiring is formed. In this method, the metal wiring layer whose surface is flat is realized, and the multilayered wiring with a high density and a high yield rate can be formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10282679A JPS5627944A (en) | 1979-08-14 | 1979-08-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10282679A JPS5627944A (en) | 1979-08-14 | 1979-08-14 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5627944A true JPS5627944A (en) | 1981-03-18 |
Family
ID=14337818
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10282679A Pending JPS5627944A (en) | 1979-08-14 | 1979-08-14 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5627944A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58127349A (en) * | 1982-01-25 | 1983-07-29 | Hitachi Ltd | Preparation of semiconductor device |
-
1979
- 1979-08-14 JP JP10282679A patent/JPS5627944A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58127349A (en) * | 1982-01-25 | 1983-07-29 | Hitachi Ltd | Preparation of semiconductor device |
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