JPS5619678A - Junction-type field effect semiconductor device - Google Patents

Junction-type field effect semiconductor device

Info

Publication number
JPS5619678A
JPS5619678A JP9501479A JP9501479A JPS5619678A JP S5619678 A JPS5619678 A JP S5619678A JP 9501479 A JP9501479 A JP 9501479A JP 9501479 A JP9501479 A JP 9501479A JP S5619678 A JPS5619678 A JP S5619678A
Authority
JP
Japan
Prior art keywords
type
region
layer
regions
diffused
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9501479A
Other languages
Japanese (ja)
Inventor
Hideki Yasuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9501479A priority Critical patent/JPS5619678A/en
Publication of JPS5619678A publication Critical patent/JPS5619678A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To obtain a back-gate-type J-FET having few I/F noises by contacting a semiconductor layer, having an opposite conducting direction with respect to a channel region, on the surface of said channel region, and limiting the thickness of the channel by a depletion layer extending from said semiconductor layer. CONSTITUTION:A back-gate-type J-FET portion 10A and NPN bipolar transistor portion 10B are provided on a P-type Si substrate 10. An N<->-type layer 11 is epitaxially grown on all the surface of the P-type Si substrate 10 through N<+>-type embeded regions 12 and 13. The layer 11 is separated into island regions 11A and 11B including the regions 12 and 13, respectively, by a P<+>-type region 14. Then, P<+>-type source and drain regions 15 and 16 and an N<+>-type gate contact region 18 are diffused and formed in the region 11A. P<+>-type base region 17, an N<+>-type emitter region 19 which is located is said region 17, and N<+>-type collector contact region 20 are diffused and formed in said region 11B. Thereafter, a P-type channel region 21 is diffused and formed in said region 11A, all the surface of the substrate 10 is covered by an SiO2 film 22, a window is opened, and an N<+>-type polycrystalline layer 23 for forming a depletion region is deposited only on the region 21.
JP9501479A 1979-07-27 1979-07-27 Junction-type field effect semiconductor device Pending JPS5619678A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9501479A JPS5619678A (en) 1979-07-27 1979-07-27 Junction-type field effect semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9501479A JPS5619678A (en) 1979-07-27 1979-07-27 Junction-type field effect semiconductor device

Publications (1)

Publication Number Publication Date
JPS5619678A true JPS5619678A (en) 1981-02-24

Family

ID=14126126

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9501479A Pending JPS5619678A (en) 1979-07-27 1979-07-27 Junction-type field effect semiconductor device

Country Status (1)

Country Link
JP (1) JPS5619678A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51128268A (en) * 1975-04-30 1976-11-09 Sony Corp Semiconductor unit
JPS5315081A (en) * 1976-07-27 1978-02-10 Nec Corp Junction type field effect transistor and its production
JPS5435689A (en) * 1977-08-25 1979-03-15 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51128268A (en) * 1975-04-30 1976-11-09 Sony Corp Semiconductor unit
JPS5315081A (en) * 1976-07-27 1978-02-10 Nec Corp Junction type field effect transistor and its production
JPS5435689A (en) * 1977-08-25 1979-03-15 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device

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