JPS5618446A - Formation of spherical salient electrode - Google Patents

Formation of spherical salient electrode

Info

Publication number
JPS5618446A
JPS5618446A JP9376079A JP9376079A JPS5618446A JP S5618446 A JPS5618446 A JP S5618446A JP 9376079 A JP9376079 A JP 9376079A JP 9376079 A JP9376079 A JP 9376079A JP S5618446 A JPS5618446 A JP S5618446A
Authority
JP
Japan
Prior art keywords
electrode
film
base
metal
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9376079A
Other languages
English (en)
Other versions
JPS6155777B2 (ja
Inventor
Hiroaki Okudaira
Toshio Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9376079A priority Critical patent/JPS5618446A/ja
Publication of JPS5618446A publication Critical patent/JPS5618446A/ja
Publication of JPS6155777B2 publication Critical patent/JPS6155777B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
JP9376079A 1979-07-25 1979-07-25 Formation of spherical salient electrode Granted JPS5618446A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9376079A JPS5618446A (en) 1979-07-25 1979-07-25 Formation of spherical salient electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9376079A JPS5618446A (en) 1979-07-25 1979-07-25 Formation of spherical salient electrode

Publications (2)

Publication Number Publication Date
JPS5618446A true JPS5618446A (en) 1981-02-21
JPS6155777B2 JPS6155777B2 (ja) 1986-11-29

Family

ID=14091380

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9376079A Granted JPS5618446A (en) 1979-07-25 1979-07-25 Formation of spherical salient electrode

Country Status (1)

Country Link
JP (1) JPS5618446A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60183315A (ja) * 1984-02-27 1985-09-18 共和機械株式会社 卵の定量包装方法
JPH02244722A (ja) * 1989-03-17 1990-09-28 Casio Comput Co Ltd 半導体素子のバンプ電極形成方法
US5244833A (en) * 1989-07-26 1993-09-14 International Business Machines Corporation Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer
US5376584A (en) * 1992-12-31 1994-12-27 International Business Machines Corporation Process of making pad structure for solder ball limiting metallurgy having reduced edge stress

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60183315A (ja) * 1984-02-27 1985-09-18 共和機械株式会社 卵の定量包装方法
JPH0260566B2 (ja) * 1984-02-27 1990-12-17 Kyowa Machine
JPH02244722A (ja) * 1989-03-17 1990-09-28 Casio Comput Co Ltd 半導体素子のバンプ電極形成方法
US5244833A (en) * 1989-07-26 1993-09-14 International Business Machines Corporation Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer
US5376584A (en) * 1992-12-31 1994-12-27 International Business Machines Corporation Process of making pad structure for solder ball limiting metallurgy having reduced edge stress

Also Published As

Publication number Publication date
JPS6155777B2 (ja) 1986-11-29

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