JPS56169323A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56169323A
JPS56169323A JP7223380A JP7223380A JPS56169323A JP S56169323 A JPS56169323 A JP S56169323A JP 7223380 A JP7223380 A JP 7223380A JP 7223380 A JP7223380 A JP 7223380A JP S56169323 A JPS56169323 A JP S56169323A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
film
substrate
section
aperture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7223380A
Other languages
Japanese (ja)
Inventor
Juichi Osuzu
Shigeru Fukuda
Masao Saito
Mitsuo Yoshioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7223380A priority Critical patent/JPS56169323A/en
Publication of JPS56169323A publication Critical patent/JPS56169323A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/221—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities of killers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To enable to supress the increase of reverse current for the subject semiconductor device by a method wherein a lifetime killer is induced into a semicoductor substrate using the insulating layer, selectively formed on one of main surfaces of the semiconductor substrate, as a mask. CONSTITUTION:An N type collector region 21, a P type base region 22, a P<+> type base contact region 23 and an N type emitter region 24 are formed on an Si semiconductor substrate and both of main surfaces of the substrate are covered by insulating films 25 an 25'. Then, an aperture 26 is formed by removing the film 25' and a part of the semiconductor substrate is exposed. Then, gold 27 is coated on the film 25' and the exposed substrate. Then, the gold 27 is diffused and induced in the semiconductor substrate by heating up the semiconductor substrate for a prescribed period of teme. At this time, when the position and the measurements of the junction of the aperture 26 and the base collector are selectively performed in such manner that the distance between the inner edge section of the aperture 26 and the section which comes in contact with the film 25 for the base collector junction will become the prescribed value or above, the gold density of the section contacting the film 25 on the base collector junction can be brought down below the prescribed value, thereby, enabling to suppress the reverse current at that section.
JP7223380A 1980-05-30 1980-05-30 Manufacture of semiconductor device Pending JPS56169323A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7223380A JPS56169323A (en) 1980-05-30 1980-05-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7223380A JPS56169323A (en) 1980-05-30 1980-05-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56169323A true JPS56169323A (en) 1981-12-26

Family

ID=13483344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7223380A Pending JPS56169323A (en) 1980-05-30 1980-05-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56169323A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62137832A (en) * 1985-12-12 1987-06-20 Matsushita Electronics Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62137832A (en) * 1985-12-12 1987-06-20 Matsushita Electronics Corp Manufacture of semiconductor device

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