JPS56168184A - Electronic timepiece - Google Patents

Abstract

PURPOSE:To ensure a supply of constant voltage regardless of a fluctuation of battery voltage and realize a stable operation of a heavy load, by backing up the battery through switching a battery voltage reducing capacitor from a series connection to a parallel connection. CONSTITUTION:Both the clock of a prescribed frequency and the delayed clock are applied to a power source control circuit 9, and the double-phase clocks are produced from AND gates 67 and 68. Then n type MOS transistor(TR) 12 and 13 of a voltage reducing circuit 10 conduct when the output of the gate 68 is set at a high level, and capacitors 12 and 13 having the same capacity are connected in series between the power sources. As a result, the battery voltage is reduced down to 1/2 to driven an elapsed time circuit or the like. While n transistors 26 and 27 conduct when the output of the gate 67 is set at a low level, and thus capacitors 12 and 13 are connected in parallel to back up the power source. The outputs of the gates 67 and 68 are set at a low level by the output Q of an FF12 of a timer circuit 82 via a heavy load circuit 7 plus the circuit 82 to be backed up by the capacitors 12 and 13 connected in parallel in the circuit 10. After this, the heavy load is stablely operated by a constant voltage circuit 8 with a constant voltage regardless of a fluctuation of battery voltage.