JPS6334993B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece, and more particularly to an electronic timepiece using a lithium battery or the like which has relatively high voltage and high internal resistance.

An object of the present invention is to provide a power supply that absorbs fluctuations in the voltage applied to the circuit due to fluctuations in battery voltage during heavy loads such as alarms and buzzers, and supplies a stable constant voltage to the clock circuit even when the battery voltage fluctuates. The object of the present invention is to provide an electronic timepiece that has stable performance even under heavy loads by providing a circuit.

In recent years, the performance of lithium batteries has improved, and some of them have begun to be used in watches, and due to the recent rise in silver prices, lithium batteries are attracting attention as batteries for watches.

Lithium batteries usually have a voltage of 3V to 2.8V,
Battery capacity for wristwatches is 60-100mAH at 3V.
It is. Complementary MOS-IC for wristwatches works well with 1.5V, so it is necessary to connect the two capacitors directly. It is well known that the life of a watch battery can be extended by creating a voltage (approximately 1.5V) that is half the battery voltage through parallel switching and driving the watch IC with this voltage. Using this method and the characteristic of lithium batteries, which have a low self-discharge rate, it is possible to create a wristwatch with a battery life of 5 to 7 years. There is a problem with high internal resistance. In particular, thin and small lithium batteries have high internal resistance and cannot be used in wristwatches with lamps or alarms.

In view of this, it is an object of the present invention to provide a power supply circuit that supplies a stable constant voltage to a clock circuit even if the battery voltage fluctuates during heavy loads such as lamps and buzzers. The aim is to achieve this by effectively using capacitors.

In the block diagram shown in FIG. 1 showing the configuration of the electronic timepiece according to the present invention, 1 is a time standard source such as a crystal oscillator, 2 is a binary frequency divider circuit, 3 is a counter circuit for seconds, minutes, hours, etc., and 4 is a decoder. , a display drive circuit; 5 is a display means such as a liquid crystal panel; 6 is a control circuit that receives signals from operation switches 14 to 17 and controls a clock circuit; 7 is a heavy-load circuit such as a lamp, an alarm buzzer, etc.; 11 is a display driving circuit; The power source is a battery. Here, assuming that the power supply battery 11 is a lithium battery and its voltage is 3V, V _DD = 0V, V _SS2
= −3V, V _SS1 = approximately −1.5V, V _DD , V _SS2 ,
The V _SS1 power supply line is shown as a dotted line. The solid lines in FIG. 1 are signal lines. 10 is a step-down circuit that steps down the battery voltage to 1/2 by switching the step-down capacitors 12 and 13 between direct and parallel switching;
is a constant voltage circuit that outputs a constant voltage even if the voltage of the power supply battery 11 fluctuates, and this voltage is set to a value close to the output voltage of the step-down circuit, that is, 1/2 of the battery voltage, 1.5V. has been done. Reference numeral 9 denotes a power supply control circuit, which normally stops the operation of the constant voltage circuit 8, operates the step-down circuit 10, and supplies the step-down voltage of the step-down circuit as the V _SS1 voltage. Meanwhile, the lamp is ON
When the heavy load circuit 7 is in operation, such as when the heavy load circuit 7 is in operation, the power supply control circuit 9 stops the operation of the step-down circuit 10, operates the constant voltage circuit 8, and supplies the stabilized voltage V _SS1 of the constant voltage circuit output. .

The reason why the constant voltage circuit 8 is always operated and the stabilized voltage of the constant voltage output is not supplied as V _SS1 regardless of the presence or absence of a heavy load is that the voltage drop of the constant voltage circuit 8 is This is because the loss is larger. That is, the step-down circuit 10 steps down the voltage by switching the capacitors 12 and 13 in series and parallel, so there is almost no step-down loss, but the constant voltage circuit 8 steps down the voltage by using the voltage drop of the MOS.TR as described later. , since we have obtained the stabilizing voltage,
Blood pressure loss is relatively large. Therefore, under normal conditions, the V _SS1 power is supplied by the step-down circuit 10 with high step-down efficiency, and the constant voltage circuit is operated only during heavy loads when it is necessary to stabilize the voltage, and the stabilized voltage is supplied as the V _SS1 power. ing.

82 in FIG. 1 is a timer circuit, and since it takes some time for the battery voltage to recover after the heavy load is removed, it continues to operate the constant voltage circuit 8 only during the timer time after the heavy load is removed. Figure 84
is a clock stop detection circuit, and when the power supply control circuit 9 stabilizes with the step-down circuit 10 operating when the battery is turned on, there is no step-down circuit clock of 1024 Hz, so no step-down output is output, and therefore there is no V _SS1 voltage. In order to prevent oscillation from starting permanently, 84 is a circuit that detects the presence or absence of a 1024Hz clock. When this circuit detects that the clock has stopped, the constant voltage circuit 8 is forcibly operated by the power supply control circuit 9. V _SS1 power supply is secured.

It should be noted that the constant voltage circuit 8 is configured to operate without the need for a clock, as will be described later.

FIG. 2 shows voltage waveforms related to the main power supply according to the block diagram of FIG. 1.

A lithium battery is used as the power supply battery 11, and the open circuit voltage is 3V, and the internal resistance of the battery is 50 to 80Ω at room temperature.
Performance is around 150-200Ω at 10℃. The heavy load is the lamp current. The left side of the vertical dotted line in FIG. 2 is the voltage waveform of each part at room temperature, and the right side is the voltage waveform of each part at low temperature.

In the figure, Sm is the lamp signal (Sw ₄ in Figure 1, 17), Sn is the output voltage of the lithium battery 11, S ₀ is the output voltage of the step-down circuit 10 in Figure 1, Sp is the output voltage of the constant voltage circuit 8, and Sq is the power supply control. This is the output voltage of circuit 9. Sn
~Sq is a voltage waveform based on V _DD , and for convenience of explanation, the step-down circuit output So and the constant voltage circuit output Sp describe the output voltage when continuous operation is performed regardless of the presence or absence of a heavy load.

As is clear from Sn in the same figure, the battery voltage is around 2V at room temperature during lamp battery current, and at low temperature.
The voltage drops to around 1.3V. Moreover, this is the voltage when about 150Ω is inserted in series with the lamp in order to reduce the lamp rush current, and if no measures are taken, the voltage during this rush will fall below 1V.

On the other hand, if the capacitor step-down circuit is operated even when the lamp is on, the step-down output will be 1/2 of the battery voltage, so as is clear from the figure So, the step-down output will drop to about 0.6V at low temperatures. , the V _SS1 system circuit does not operate at this voltage. To cover this voltage drop, the step-down circuit output is normally used as the V _SS1 power supply, and during heavy loads the battery voltage is directly supplied to V _SS1.
There is also a method of using it as a power source, but with this method, as is clear from Sn, the battery voltage fluctuates significantly depending on the temperature, so when the load is heavy, the V _SS1 power source also fluctuates accordingly, which can cause malfunctions. Possible malfunctions include counting errors and resetting of the counter circuit due to sudden voltage fluctuations.Also, under heavy loads under relatively high temperature conditions, the battery voltage does not drop much and the voltage close to 3V is V _SS1. Since it is supplied to the power supply, there is a risk that the crystal oscillation circuit will cause harmonic oscillation.

In comparison, the constant voltage circuit output is Sp
As is clear from the voltage waveform, the voltage remains constant as long as the battery voltage does not fall below the output setting voltage of the constant voltage circuit, and when the battery voltage falls below the setting voltage,
The battery voltage is directly output as the output of the constant voltage circuit.

Therefore, as mentioned above, under normal conditions, the step-down circuit 10
If the power supply control circuit 9 is configured so that the output of the constant voltage circuit 8 is used as the V _SS1 power supply and the output of the constant voltage circuit 8 is used as the V _SS1 power supply during heavy loads, the voltage shown in Fig. 2 Sp is supplied as the V _SS1 power supply. . In Sq, the solid line is supplied with the output of the step-down circuit 10, and the dashed line is supplied with the output of the constant voltage circuit 8.
Indicates that the output is being supplied. Sr indicates the time during which the constant voltage circuit 8 is operating, and Ss measures a certain period of time after the heavy load is released. Timer circuit 8
It represents the time for the second action. Due to this timer operation, after the heavy load is removed and the battery voltage has completely recovered, the V _SS1 power supply shifts from constant voltage output to step-down output. Note that there are places where the voltage momentarily drops in the V _SS1 voltage Sq, but this is because the battery voltage has fallen below the constant voltage setting voltage.
As mentioned above, by inserting a resistor in series with the lamp or selecting an appropriate lamp, it is possible to suppress the voltage to around 1.3V, which is a level that does not cause any practical problems.

As described above, under the control of the power supply control circuit 9, the capacitor step-down circuit 10 operates under normal conditions.
V _SS1 power can be supplied with step-down conversion efficiency close to 100%,
During heavy loads where the battery voltage fluctuates significantly, and when heavy loads are released, the constant voltage circuit 8 and timer circuit 82 operate to supply a stable voltage as the V _SS1 power source.

As an embodiment of the electronic timepiece according to the present invention, a circuit diagram related to the power supply circuit is shown in FIG. 3, and a main timing chart thereof is shown in FIG. 4.

In FIG. 3, the block 8 within the dotted line corresponds to the constant voltage circuit 8 in FIG. In addition, block 82 corresponds to the timer circuit 82, and block 84 corresponds to the clock stop detection circuit 84.
Block 83 is part of power supply control circuit 9 and forms a delay circuit.

In FIG. 3, 18 to 28 are P.MOS.FETs, only 25 is a depletion type, and the others are all enhancement types. 29-37 are enhancement type N.MOS.FET, 41-4
8 is a switching gate, and the gate potential
It is conductive when it is high and non-conductive when it is low.

All gates other than those mentioned above, Flip/Flop (F/F), are composed of complementary MOS/FETs. 38,
39 is a capacitor with a built-in IC, 40 and 8
Similarly, 5 to 87 are resistors built into the IC. 51~
61 is a master-slave FF, 62 and 64 are slave type half FFs, and 63 is a master type half FF, and in all cases the master is CLOCK=
Write state when High, slave is CLOCK = Low
It enters the writing state. In Figure 3, 17 is a lamp lighting switch as an external element outside the IC.
Sw ₄ , 78 is for lamp, 79 is for alarm drive
NPN transistor, 80 is the same inductance,
81 is a piezoelectric element, and 12 and 13 are step-down capacitors (approximately 0.1 μF).

In Fig. 3, the 1024HzD signal is a signal obtained by delaying the 1024Hz signal by a time such as 1/32768 seconds or _{1/16384 seconds} . 3. Make a two-phase clock for a step-down circuit as shown in Figure 3. MND gates 67A ₃ and 68A ₄ , when the timer circuit output F ₁₂ Q becomes High (that is, during heavy load and when the timer circuit is operating after heavy load is released),
Both A ₃ and A ₄ gate outputs are configured to be low as shown in FIG. 4 A ₃ and A ₄ .

To explain the operation of the step-down circuit 10, A ₄ is High
(Figure 4 A ₄ perspective part) N・MOS・FET35,
36 becomes conductive, and capacitor 12C _A and capacitor 13C _B are connected in series between the V _DD and V _SS2 power supplies. Since C _A and C _B have the same capacitance, V _SS1
A voltage that is half the battery voltage will be applied. On the other hand, A ₃ is Low (A ₃ shaded area in Figure 4)
At this time, the P-MOS-FETs 26 and 27 become conductive, and C _B is connected in parallel with C _A between V _DD and V _SS1 to supply the charged charge to the V _SS1 system.

In Figure 4, A ₃ shaded area (C _A and C _B are parallel)
It can be seen that under normal conditions without heavy load, the shaded area of A4 and _A4 (in series with C _A and C _B ) are alternately repeated at a cycle of 1024 Hz, resulting in a voltage drop. The reason why the phases of the shaded parts A ₃ and A ₄ are shifted and the voltage is stepped down by a two-phase clock is that when switching, the combination of transistors 26 and 35, or 27 and 36, 35 and 27, or 26 and 36 This is to prevent short circuit between the power supplies or loss of charge in C _B due to conduction. If a step-down circuit is driven by a single-phase clock without this improvement, a step-down loss current of 0.1 to 0.2 μA will occur, depending on the size of the step-down transistor.
Confirmed by experiment.

On the other hand, when a heavy load such as a lamp is on, the _step -down operation stops and C _A
and C _B are connected in parallel between V _DD and V _SS1 , and function as a power supply backup capacitor for the V _SS1 system.

In addition, when the heavy load is turned on, C _A and C _B are instantly connected in parallel to V _SS1 , and due to the function of the delay circuit 83, after the heavy load is turned on, for about 1 mS until the constant voltage circuit stabilizes, , supply the V _SS1 power with the charging charges of C _A and C _B. This is C _A and C _B instantaneously when heavy load is ON.
If C _A and C _B are connected in series between V _DD and V _SS2 without being connected in parallel, a voltage drop as shown in Figure 2 So will be supplied to the V _SS1 power supply, causing malfunction.

Furthermore, in this embodiment, after the heavy load timer is turned off, when transitioning from constant voltage output to step-down circuit operation, C _A is always activated.
and C _B are connected in series, and measures have been taken to minimize voltage fluctuations.

Block 83 is a delay circuit having the above-mentioned function, and as shown in FIG. 4 F ₁₃ Q and F ₁₄ Q, the signal is delayed with respect to F ₁₂ Q and becomes the signal A ₅ . When F ₁₂ Q = Low, the constant voltage circuit is turned on, and when A ₅ = High, the V _SS1 power is supplied from the constant voltage circuit side, and the delay relationship is clear from FIG.

Block 87 is a timer circuit, which uses the 1Hz signal from _F10 as a clock, and normally outputs _F12 when the low lamp or alarm is ON, and when the alarm is on.
Approximately 1.5 seconds after OFF and clock stop detection circuit 84
While the clock is determined to be stopped, and for about 1.5 seconds after the clock is released, the _F12 output becomes High, and the constant voltage circuit 8 is operated.

Block 84 is a clock stop detection circuit.
It operates as shown in the timing chart in Figure 5.
The circuit output Se is low during normal operation and high when the clock is stopped.

The third block 8 is a constant voltage circuit, and is a MOS/
FET18, 19, 29, and 30 constitute a reference voltage source, and MOS/FET20 and 31 constitute a MOS/FET
A bias circuit for operating 21 and 24 at a constant current is formed. MOS・FET21~23,3
2 and 33 form a differential amplifier circuit,
The MOS/FETs 24 and 34 form an amplifier circuit. MOS/FET25 is for voltage control
It is a TR and uses depletion mode P/MOS/FET in source follow so that self-feedback is applied. Resistors 85 to 87 are voltage dividing resistors for setting output voltage values.

The reference voltage source is the gate part of N・MOS・FET29
By doping Polg-Si with P impurity,
N-MOS-FET doped with N impurity
It is created by using the difference in the threshold voltage V _TH of each transistor due to the difference in the work function of the Gate electrode between the _drain of FET 19 and _V Voltage,
Approximately 1V appears.

Here, assuming that the reference voltage is V _ST , the resistor voltage division ratio by resistors 85 to 87 is A, and the constant voltage circuit output voltage is V _SS1 , feedback is applied so that V _ST = A × V _SS1 and balanced. The gate bias of the control FET 25 is automatically set. If _VST is 1V and _VSS1 is 1.5V, which is equal to the step-down circuit output voltage, then A=1/1.5.

In this embodiment, while the clock stop circuit 84 determines that the clock is stopped, the switching gate 47 becomes conductive and the resistance voltage division ratio A decreases to 1/1.
1.7, and V _SS1 is 1.7V, which is slightly higher than the conduction voltage.
The crystal oscillation circuit has been devised to improve its self-starting performance.

Furthermore, when the load is heavy, the battery voltage drops and the effective driving voltage of the liquid crystal display element drops, making it difficult to see the liquid crystal, so the constant voltage circuit output during heavy loads is intentionally set to a high value such as 0.7V. It is possible to increase the effective voltage for driving the liquid crystal to make it easier to see. However, there is no change in contrast, and some DC components remain, but this is within a range that poses no practical problem.

As described in detail above, according to the present invention, by effectively using a step-down capacitor even when the constant voltage circuit is operating, it is possible to effectively use the step-down capacitor even when the step-down circuit and the constant voltage circuit are switched, and even when heavy loads such as lamps and alarms are being applied. Since a stable voltage can be supplied to the clock circuit and high step-down efficiency can be obtained under normal conditions, a clock system with long battery life and no malfunctions can be realized.

Although the embodiments have been explained using lithium batteries, the present invention is not limited to electronic watches using lithium batteries, and the present invention can also be applied to electronic watches using other batteries with relatively high voltage. is applicable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the structure of an electronic timepiece according to the present invention. FIG. 2 is a diagram showing voltage waveforms related to main power sources in the block diagram of FIG. 1. FIG. 3 is a circuit diagram related to a power supply circuit in an embodiment according to the present invention. FIG. 4 is a timing chart of the main parts of the circuit diagram in FIG. 3. FIG. 5 is a timing chart of the main parts of the clock stop detection circuit 84. 1... Crystal oscillator, 2... Frequency dividing circuit, 3... Counter, 4... Decoder, drive circuit, 5...
Display element, 6...control circuit, 7...heavy load circuit,
8... constant voltage circuit, 9... power supply control circuit, 10...
. . . step-down circuit, 82 . . . timer circuit, 84 . . . clock stop detection circuit.

Claims (1)

[Claims] 1. An electronic circuit comprising a power supply battery, a step-down circuit that steps down the battery voltage of the power supply battery by switching a plurality of capacitors in series/parallel, a time standard source/frequency divider circuit, etc., and uses the step-down voltage from the step-down circuit as a driving power source;
a heavy load circuit receiving voltage supply from the power supply battery;
a constant voltage circuit that forms a constant voltage based on the battery voltage of the power source battery; receiving a drive signal from the heavy load circuit; and switching the drive power source of the electronic circuit from the step-down voltage to the constant voltage;
An electronic timepiece comprising a power supply control circuit that connects the plurality of capacitors in parallel to the drive power supply.