JPS5815183A - Multi-function electronic clock - Google Patents

Abstract

PURPOSE:To prevent a malfunction of a circuit, by controlling a timing of turn-on of a switching transistor and driving of a pendulum and preventing a voltage drop due to pendulum driving of the second electric power supply which has used a charge storage member. CONSTITUTION:A clock circuit 13 is operated by using a capacitor 12 charged through a switching transistor 16, as the second electric power supply. Also, a pendulum device 14 is driven by a signal 15. A signal 17 for driving the switching transistor 16, and the signal 15 for driving the device 14 are formed by a delaying circuit of 2 stages consisting of inverters 34, 35, resistances R1-R4 and capacitors C1, C2, and superposition of turn-on of the switching transistor 16 and driving of the device 14 is prevented.

Description

[Detailed description of the invention] The present invention relates to a switching transistor (hereinafter referred to as a switching transistor).

The present invention relates to a multi-functional electronic watch that has two power supplies and a heavy load device connected in parallel via a 8W transistor (abbreviated as Tr), and relates to a drive system for the 8W transistor and a heavy load device.

The purpose of the present invention is to control the timing between BY and TER OW and heavy load drive, and to reduce the voltage drop due to the single load drive IIC of the second power supply by using a charge storage member (hereinafter abbreviated as a capacitor). The objective is to find a method to prevent circuit malfunctions.

Figure 1 shows two 13W transistors connected in parallel via a Tr.
1 is a schematic diagram of a multifunctional watch with two power sources and heavy load devices;

In Figure 1, 11 is a battery b 12 tf
Each of these is used as a power source. 13#
i is a clock circuit, includes 1 oscillation circuit, 1 branch circuit, counter*1 control circuit, etc., and connects VDD to ground at b.
It operates using SGM as a power source. 14ij heavy load device, 611t 8W, T, which is driven when the signal 15 is at the "■work" level, with VDD as ground and VSS as the power supply.
It is r.

17 signal 1 (zJ) ON, O'F? l, When it is ON, the two power supplies, the battery power supply and the capacitor power supply, are shorted, and when it is OFF, the two are separated and used as separate power supplies.

This is the inverter electric flit188B.

t112 diagram #'i, heavy load drive and 8W, ? This book shows the state of VSS and VB8B when the ON times of , overlap due to factors such as element delay.

In Figure 2, jd r te, 15 e 17, ”18
B, VBBBJd It is similar to Fig. 1, and VBB,
mtn is the potential of VSS when no voltage drop occurs. Also, t is the delay caused by the inverter, and 21#
This is the lowest operating level of the i-clock circuit 13. Signal 15 is “
When the heavy load 14 is driven in the state of "H", an L-stain voltage drop occurs in the drive current of the power supply Vss, resulting in a potential as shown in the figure. Also, signal 17 is "R engineering" and signal 11 is 13W,
Since Tr is am-(vss and mer u1 are in contact with each other, a voltage drop occurs in the same way as 1VB8BFiVBB,
When the signal 17 becomes "LO", the SW and Tr turn OFF, the potential at the fall of the signal 17 is held, and then a gradual voltage drop occurs due to the current consumption of the circuit 13. At this time, v81 when the voltage drop exceeds the minimum operating level 21 of the circuit 13.

The clock malfunctions or stops. I again. 8W,'r
It can also occur due to turning on of r, heavy shush of quadruple load drive ``''-Tr+switching delay of heavy load device.

This invention F! , which looks at the problems listed in item a and provides a method to eliminate them. A detailed description of the present invention will be added below in one drawing.

FIG. 3 shows a specific example of the electronic circuit of the electronic timepiece according to the present invention and its timing chart.

In FIG. 3 h, 11 to 17 are the same as in FIG. 1.

31 is a heavy load drive signal obtained from the clock circuit 13, and corresponds to signal 15 in FIG. It is a 34.35 fl inverter, and its power is obtained through resistors R1 to R4, and capacitors C,, C, are connected to the output line, and 2
The stage delay circuit is left alone. Also, note the other gauges in particular, and #f-1 is the power supply system HV88B. Now, when a signal as shown in the timing chart is output to 31, the delay circuit 34 generates a signal 32 with rising and falling edges corresponding to the time constants of the resistors R, , R and capacitor Cs. It will be done. Since this haze exceeds the threshold hold of the next-stage inverter with a delay with respect to signal 31, a signal like 15 can be generated. The delay circuit in the next stage is also used to generate a signal. to this! ,0.17
It is possible to generate a signal such as This 15, 17
If you drive an 8W, Tr and heavy load using this signal,
Van*V81! It becomes like Bt[I. vgsit series V
When the ss system is set to a -h, be sure to set VsB Iri
When the voltage is restored to a potential with no voltage drop, since the capacitor 12 and the current consumption KL of the circuit are sufficiently large, vB8BFi will not be determined and the lowest operating level 4 of the circuit will not occur.

Therefore, it is possible to prevent the °C1 clock from malfunctioning or stopping. Also, since the DELAT T engineering Ml of the element is relatively short.

The resistance and capacitance used in the delay circuit can be small and integrated circuits (
IC) It is also possible to incorporate K. Sara (CRt=
-R3 lines R@=R4, C@xm By using G snow, it is also possible to make the signal 31 and the signal 15 have exactly the same shape. Also, when the power is turned on, the capacitance CIK indicates that the blade is “L”.
Since it is pulled by ol, 15 also becomes "LO" and one load is not driven, which can be an advantageous condition for starting one oscillation.

FIG. 4 is another specific example of the electronic circuit of the electronic timepiece according to the present invention and its timing chart.

In FIG. 4, numbers 11 to 17 are the same as in FIG.

41 is a heavy load drive signal obtained from the clock circuit 13, and corresponds to signal 15 in FIG. Reference numeral 45 is a master type e-latch that releases a two-stage delay circuit, and corresponds to the delay circuit 35 in FIG.

A point not mentioned in particular is the power supply system ij V88B for each element. Its operation is as shown in the timing chart, and using signals 15 and 17 obtained from this circuit,
When driving 8W, Tr and heavy load, Vas・Wa
sB will be similar to that shown in FIG. Further, the delay circuit designed with a digital circuit is not limited to this embodiment.As mentioned above, if one of the present invention is applied, a simple timing circuit or delay circuit can be constructed with four circuits and a large voltage of V8BB. It eliminates voltage drops and prevents the clock from malfunctioning or stopping. [L
8W, the delay time to prevent the ON of the Tr and heavy load driving from overlapping can be determined by changing the constants of the resistors R, ~R4 and the capacitors CI and C, as shown in Figure 4. In the example above, it can be easily changed by changing the frequency of CL.Furthermore, at the moment when the SW and Tr are turned on and the heavy load drive goes to 0IFIF, val immediately returns to the circuit minimum operating level or higher. Therefore, if it is a short period of time, it is acceptable.

It is a particularly effective means for a multifunctional electronic watch that has the Fi of the present invention, an electric-to-mechanical converter, a lighting device, a sound generator, etc., and has two power supplies connected in parallel via SW and 'RY. get it.

[Brief explanation of the drawing]

Stripe Figure 1...Circuit diagram of a multi-function electronic watch with two power supplies and heavy load devices connected in parallel via sv and 'rde.Figure 2...In the circuit of Figure 1, B'il, Timing chart when Tr ON and heavy load driving overlap Fig. 3 1t0LH61...Specific example of the electronic circuit of the electronic clock according to the present invention [α1 and its timing chart h (6
) Fig. 4 1tLHb) - Another specific example of the electronic circuit of the electronic watch according to the present invention (Q3 and its timing diagram 1b)
1 or above Applicant Suai Seikosha Co., Ltd. Agent Mogami

Claims (1)

[Claims] 16 A charge storage member connected in parallel with a battery as a first power source via a switching transistor (SV, Tr) is provided as a power source for the first power source. When driving one or more of the heavy load devices that require a drive current that is large enough to cause a voltage drop in the power supply, #i BW
, fr 01P L, ! In a multi-function electronic watch, the power supply of 1 and the power supply of iris 2 are separated, the first power supply is used as a power source for heavy load, and the power supply of I[2 is used as a power supply for other circuits. A multifunctional electronic timepiece designed to have a tie-2nd circuit or a delay circuit for the purpose of temporally delaying the driving of the 01 and the heavy load AT to prevent the overlap between the two. 2. A multifunctional electronic timepiece according to Claims 111, in which the heavy load device is an electro-mechanical converter, a light device, or a sound generator.