JPS63228094A - Electronic timepiece - Google Patents

Abstract

PURPOSE:To supply a stable voltage to a circuit for a timepiece so as to extend a battery life and to prevent malfunction by operating a voltage drop circuit during non-operation of a heavy load circuit and operating a constant voltage circuit during operation of the heavy load circuit. CONSTITUTION:A voltage drop circuit 10 drops a battery voltage to 1/2 by series-parallel switching of capacitors 12, 13 for voltage drop. The constant voltage circuit 8 outputs a specified voltage in spite of a fluctuation in the voltage of the source battery 11 and is normally set at the value approximate to the output voltage of the voltage drop circuit 10. A power supply control circuit 9 normally supplies the dropped voltage from the circuit 10 by stopping the operation of the circuit 8 and supplies the stabilized voltage from the circuit 8 by stopping the operation of the circuit 10 and operating the circuit 8 during the operation of the heavy load circuit 7 such as alarm or buzzer. The circuit 8 is forcibly operated to assure the stabilized power supply by the operation of the circuit 9 when a clock stop detecting circuit 84 for detecting the presence or absence of the clock of the voltage drop circuit detects the clock stop.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic watch, and in particular, a watch with a relatively high voltage.
Moreover, it relates to an electronic watch using a lithium battery or the like, which has a large internal resistance.

The purpose of the present invention is to absorb fluctuations in circuit applied voltage due to fluctuations in battery voltage during heavy loads such as alarms and buzzers,
To obtain an electronic timepiece having stable performance even under heavy load by providing a power supply circuit that supplies a stable constant voltage to a timepiece circuit even when battery voltage fluctuates.

An object of the present invention is to provide an electronic watch that uses a lithium battery or the like and supplies the voltage of the battery lowered by a step-down circuit to a watch circuit, so that when the battery is inserted, the crystal oscillation circuit reliably starts oscillating without any external operation, and the watch starts operating. The purpose is to provide a system that starts automatically.

In recent years, the performance of lithium batteries has improved, and some of them have begun to be used in watches, and due to the recent rise in the price of silver, lithium batteries are attracting attention as batteries for watches.

Lithium batteries usually have a voltage of 3v to 2.8v, and the battery capacity is 60 to 100 mAH for a 3 inch watch battery.
It is. Complementary MO3-IC for wristwatches works well with 1.5V, so by switching between series and parallel switching of the two capacitors, the voltage is half the battery voltage (approximately 1.5V).
It is well known that the battery life of a watch can be extended by generating this voltage and driving a watch IC with this voltage.

Using this method and the characteristic of lithium batteries, which have a low self-discharge rate, it is possible to create a wristwatch with a battery life of 5 to 7 years. There is a problem with high internal resistance. In particular, thin and small lithium batteries have high internal resistance and cannot be used in wristwatches with lamps or alarms.

Furthermore, the aforementioned step-down circuit cannot step down the voltage without a step-down clock, and on the other hand, the crystal oscillator cannot start oscillating without power supply from the step-down circuit, so it has the problem that it does not start up automatically when the battery is inserted. .

In view of this, the present invention provides a power supply circuit that supplies a stable constant voltage to a clock circuit even if the battery voltage fluctuates during heavy loads such as lamps and buzzers, and also ensures self-starting when the battery is turned on. It provides a system to get started.

In the block diagram shown in FIG. 1, which shows the configuration of an electronic timepiece according to the present invention, 1 is a time standard source such as a crystal oscillator, 2 is a binary frequency divider circuit, 3 is a counter circuit for seconds, minutes, hours, etc. 5 is a decoder/display drive circuit; 5 is a display means such as a liquid crystal panel; 6 is a control circuit that receives signals from operation switches 14 to 17 and controls the clock circuit;
7 is a heavy load circuit such as a lamp, an alarm, a buzzer, etc., and 11 is a power source battery. Here, the power supply battery 11 is a lithium battery,
Assuming the sono voltage is 3V, Voo=OV, VSS, =-
3V, VSSI - as approximately -1,5V, V D D
5V3st, VSSI 1! The source line is represented by a dotted line.

The solid lines in FIG. 1 are signal lines. 10 is a step-down circuit that switches the step-down capacitors 12 and 13 between series and parallel switching to step down the battery voltage to B; 8 is a power supply battery 1;
This is a constant voltage circuit that outputs a constant voltage even if the voltage of the voltage converter 1 fluctuates, and this voltage is set to a value close to the output voltage of the step-down circuit, that is, 1°5V, which is % of the battery voltage. Reference numeral 9 denotes a power supply control circuit, which normally stops the operation of the constant voltage circuit 8, operates the step-down circuit 10, and supplies the step-down voltage of the step-down circuit as the VSS+ voltage. On the other hand, when the heavy load circuit 7 is in operation, such as when the lamp is turned on, the power supply control circuit 9
35. stops the operation of the step-down circuit 10 and operates the constant voltage circuit 8 to obtain the stabilized voltage of the constant voltage circuit output.
Supplied as voltage.

The reason why the constant voltage circuit 8 is always operated and the stabilized voltage of the constant voltage output is not supplied as VSSI regardless of the presence or absence of a heavy load is that the step-down loss of the constant voltage circuit 8 is lower than that of the step-down circuit 10. This is due to the fact that is larger. That is, the step-down circuit IO steps down the voltage by switching between series and parallel switching of the capacitors 12 and 13, so there is almost no step-down loss, but the constant voltage circuit 8 steps down the voltage by using the voltage drop of the MOS-TR as described later. Since a stabilized voltage is obtained, the step-down loss is relatively large. Therefore, under normal conditions, the Vss+ power source is supplied by the step-down circuit 10 with high step-down efficiency, and the constant voltage circuit is operated only during heavy loads when it is necessary to stabilize the voltage, and the stabilized voltage is supplied as the V3s1 power source. .

82 in FIG. 1 is a timer circuit, and since it takes some time for the battery voltage to recover after the heavy load is removed, the constant voltage circuit 8 continues to operate for only one hour after the heavy load is removed. 84 in the figure is a clock stop detection circuit,
If the power supply control circuit 9 is stable in operating the step-down circuit IO when the battery is turned on, the step-down circuit clock is 1024Hz.
84 is a circuit that detects the presence or absence of the 1024 + (z clock, and this circuit detects the presence or absence of the clock. When detected, the constant voltage circuit 8 is forcibly operated by the function of the power supply control circuit 9 to secure the vssl power supply.The constant voltage circuit 8 is configured to operate without the need for a clock, as will be described later. .

Figure 2 shows the voltage waveforms related to the main power supply according to the block diagram in Figure 1.A lithium battery is used as the power supply battery 11, the open circuit voltage is 3V, and the internal resistance of the battery is 50 to 80Ω at room temperature. The performance is about 150 to 200Ω at 10°C. The heavy load is the lamp current. The left side of the vertical dotted line in FIG. 2 is the voltage waveform of each part at room temperature, and the right side is the voltage waveform of each part at low temperature.

In the figure, Sm is a ramp signal (173W4 in Figure 1), Sm is the output voltage of the lithium battery 11, and So is the step-down circuit 10 in Figure 1.
, Sp is the output voltage of the constant voltage circuit 8, and Sq is the output voltage of the power supply control circuit 9. Sm-3q is ■. This is a reference voltage waveform, and for convenience of explanation, the step-down circuit output So and the constant voltage circuit output Sp are described as output voltages when continuous operation is performed regardless of the presence or absence of a heavy load.

As is clear from Sm in the same figure, during lamp rush current, the battery voltage drops to about 2V at room temperature, and drops to about 1.3V at low temperature. Moreover, this is the voltage when about 1000 lamps are inserted in series to eliminate the lamp rush current, and if no measures are taken, the voltage during this rush will fall below 1V.

On the other hand, if the capacitor step-down circuit is operated even when the lamp is lit, the step-down output will be 2 times the battery voltage, so as is clear from So in the figure, the step-down output will drop to about 0.6 V at low temperatures. The V11m1 system circuit does not operate at this voltage. To cover this voltage drop,
There is also a method of using the step-down circuit output as a V1$1 power supply during normal times, and using the battery voltage directly as a source of Vssl during heavy loads, but with this method, as is clear from Sm, the battery voltage fluctuates significantly depending on the temperature. 1.1 When the load is heavy, the power supply will also fluctuate, causing malfunctions. Possible malfunctions include counter circuit miscounts and resets due to rapid voltage fluctuations, and battery voltage drops significantly under heavy loads under relatively high temperature conditions. Since it is supplied to the I power supply, there is a risk that the crystal oscillation circuit will cause harmonic oscillation.

In comparison, the constant voltage circuit output is a constant voltage unless the battery voltage falls below the output setting voltage of the constant voltage circuit, as is clear from the power supply waveform in Figure 2 Sp. Then, the battery voltage is directly output as the output of the constant voltage circuit.

Therefore, as mentioned above, under normal conditions, the output of the step-down circuit 10 is
, 1. For the power supply, when the load is heavy, the output of the constant voltage circuit 8 is set to V s
If the power supply control circuit 9 is configured to use the s+ power source, the voltage shown in FIG. 2 sq is supplied as the V1m+ power source. In Sq, the solid line indicates that the output of the voltage down converter 10 is supplied, and the dashed line indicates that the output of the constant voltage circuit 8 is supplied. Sr indicates the time during which the constant voltage circuit 8 is operating, and Ss measures a certain period of time after the heavy load is released. Due to this timer operation, which represents the operating time of the timer circuit 82, after the heavy load is removed and the battery voltage is completely recovered, the power supply is shifted from the constant voltage output to the step-down output. Note that there are places where ■, □ voltage is S, and the instantaneous voltage drops, but this is because the battery voltage has fallen below the constant voltage setting voltage, so as mentioned above, insert a resistor in series in the lamp. 1.3V, which is at a level that does not cause any practical problems, can be achieved by
It can be kept to a minimum.

As described above, under the control of the power supply control circuit 9, the capacitor step-down circuit 10 normally operates and can supply Vss power with a step-down conversion efficiency close to 100%, and during heavy loads when the battery voltage fluctuates significantly, When the heavy load is released, the constant voltage circuit 8 and the timer circuit 82 operate to supply a stable voltage as the Vss+ power source.

As an embodiment of the electronic timepiece according to the present invention, a circuit diagram related to the power supply circuit is shown in FIG. 3, and a main timing chart thereof is shown in FIG. 4.

In FIG. 3, the block 8 within the dotted line corresponds to the constant voltage circuit 8 in FIG.
corresponds to the heavy load circuit 7, the block 82 corresponds to the timer circuit 82, and the block 84 corresponds to the clock stop detection circuit 84.

Block 83 is part of power supply control circuit 9 and forms a delay circuit.

In FIG. 3, 18 to 28 are P-MOS-FETs, only 25 is a depression type, and the others are all enhancement types. 29 to 37 are enhancement type N-MO3-FETs, and 41 to 48 are switching gates, which are conductive at the gate potential) high and low at the same gate potential.
It is non-conductive at w.

Gates other than the above, Fl 1p-Flop (F-F)
The series are all composed of complementary MO3-FETs.

38.39 is a capacitor with built-in IC, 40 and 8
5 to 87 are the same resistors built into the IC.

51 to 61 are master-slave FFs, 62.64 are slave type half FFs, and 63 are master type half FFs, and in all cases the master is CLOCK-High.
When CLOCK=Low, the slave enters the write state. In Fig. 3, the external elements outside the IC are as follows: 17 is a lamp lighting slit (SW4), 7B is a lamp, 79 is an alarm driving NPN transistor, 80 is an inductance, 81 is a piezoelectric element, 12.
13 is a step-down capacitor (approximately 0.1, 17F).

In Figure 3, the 1024HzD signal is 1024Hz
It is a signal that is delayed by a time such as 1/32768 seconds or 1/16384 seconds, and 1024) (z and 10
Using a 24Hz D signal and using the same <66 (Ai) as the AND gate 65 (AI), create a two-phase clock for the step-down circuit as shown in Figure 3.AND gate 1-67 (A3)
68 (A,), when the timer circuit outputs F and tQ become High (that is, during heavy load and when the timer circuit is operating after heavy load is released), both As and As gate outputs become as shown in Fig. 4 A3 and A4. It is configured so that it becomes Low.

To explain the operation of the step-down circuit 10, when A4 is Hlgh (shaded area A4 in Figure 4), N-MOS-FET35.36
becomes conductive, and when capacitor 12 (CA) and capacitor 13 (C++) are in series, V DD V
Connected between ssz power supplies. Since C^ and C1 have the same capacity, a voltage obtained by dividing the battery voltage into two is applied to vs□. On the other hand, when A is Low (Fig. 4 A, shaded area), P-MOS-FET26.27 becomes conductive, C6 is connected in parallel with CA between VDII vsst, and the charge charged in the VSS1 system is connected. supply.

In Figure 4, the A3 shaded area (Ca and Cm are parallel) and the A3
It can be seen that the four shaded areas (CA, C8 series) are alternately repeated at 1024 Hz F1 period and the voltage drops under normal conditions without heavy load. Note that the phases of the shaded areas of Ax and A4 are shifted, and the reason why the voltage is stepped down using a two-phase clock is that when switching, transistors 26 and 35, or 27 and 36.3
This is to prevent the transistors of the combinations 5, 27, 26, and 36 from conducting, thereby preventing transfer between the power supplies or loss of charge in C8. It has been experimentally confirmed that if a step-down circuit is driven by a partial clock without this improvement, a step-down loss current of 0.1 to 0.2 μm occurs, depending on the size of the step-down transistor.

On the other hand, when there is a heavy load such as a lamp at 08, as is clear from the shaded area in FIG. 4A, the step-down operation stops and C1 and C are connected in parallel. -7887, and functions as a power supply backup capacitor for the ■ and □ systems.

Also, when the heavy load is turned on, CA and C1l are instantly connected in parallel to V351, and due to the function of the delay circuit 83, it takes about 1 m until the constant voltage circuit stabilizes after the heavy load is turned on.
During the period s, the VSS+ power is supplied by the charged charges of CA and C3. When this heavy load is turned on, CA and C3 are not connected in parallel instantly, and VDD and ■! If CA and CI are connected in series between 2 and 2, a voltage drop as shown in So in FIG. 2 will be supplied to the v3,1 power supply, causing malfunction.

Furthermore, in this embodiment, when transitioning from constant voltage output to step-down circuit operation after the heavy load timer is turned off, CA and 06 are always connected in series, and measures have been taken to minimize voltage fluctuations. It is.

Block 83 is a delay circuit having the above-mentioned function, and the fourth
FI as in Figure F 1sQ, F +-Q! It is delayed with respect to Q and becomes a signal of A. e F+z When Q=Low, the constant voltage circuit turns ONL, and when As=High, it becomes V.

1 power is supplied from the constant voltage circuit side, and the delay relationship is clear from FIG.

Block 82 is a timer circuit, F. IH from
Using the z signal as a clock, the F1□Q output is normally L.
o w, when the lamp or alarm is on, and when the same is off
After about 1.5 seconds, while the clock stop detection circuit 84 determines that the clock has stopped, and for about 135 seconds after the cancellation, the F+zQ output becomes High and the constant voltage circuit 8 is operated.

Block 84 is a clock stop detection circuit, which operates as shown in the timing chart of FIG.

The circuit output si is Low during normal operation and High when the clock is stopped.
It becomes igh.

Block 8 in Fig. 3 is a constant voltage circuit, which includes MOS/FET
18, 19, 29.30 constitute a reference voltage source, and MO
The S-FETs 20 and 31 form a bias circuit for operating the MOS-FETs 21 and 24 at constant current. M
A differential amplifier circuit is formed by the OS and FETs 21 to 23, 32, and 33, and an amplifier circuit is formed by MOS-FETs 24 and 34. MOS-FET 25 is a voltage control TR, and a depressin mode P-MO3-FET is used in source follow so that self-feedback is applied. Resistors 85 to 87 are voltage dividing resistors for setting output voltage values.

The reference voltage source is the Gate of N-MOS-FET29.
N-MOS-FET3 doped with N impurity by doping P impurity in the part Po1y-5t
Due to the difference in the work function of the Ge ta electrode between 0 and
Threshold voltage VT+ of each transistor
4 is made using the difference between the drain of FET19 and ■,
. Between VT14 of FET 29 and VT14 of FET 30, a voltage of about 1■ appears.

Here, if the reference voltage...■, A, the resistor voltage division ratio A due to resistors 85 to 87, and the constant voltage circuit output voltage...■5,1, the feedback is set so that Vst=AXVss+ and balance is maintained. Then, the gate bias of the control FET 25 is automatically set. VS
t is 1■, vssr is 1.5 equal to the step-down circuit output voltage.
When V, A=1/1.5.

In this embodiment, while the clock stop circuit 84 determines that the clock is stopped, the switching gate 47 becomes conductive and the resistor voltage division ratio A decreases to 1/1.7, so that V f
The f31 voltage is a little higher than the normal voltage, about 1.7 cm, and is designed to improve the self-starting performance of the crystal oscillation circuit.

Furthermore, when the load is heavy, the battery voltage drops, so the effective driving voltage of the liquid crystal display element drops and the liquid crystal becomes invisible. It is possible to increase the effective voltage for driving the liquid crystal and make it easier to see.However, there is no change in contrast and a slight DC component remains, but this is within a range that poses no practical problem.

As detailed above, according to the present invention, the crystal oscillation circuit can reliably start automatically when the battery is inserted, and even when the battery voltage fluctuates significantly during heavy loads such as lamps and alarms, the clock circuit remains stable. can supply a stable voltage and achieve high step-down efficiency under normal conditions, making it possible to create an easy-to-use clock system with long battery life and no malfunctions.

Although the embodiments have been explained using lithium batteries, the present invention is not limited to electronic watches using lithium batteries, but is also applicable to electronic watches with step-down circuits using other batteries with relatively high voltage. The present invention is also applicable to watches.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an electronic timepiece according to the present invention. FIG. 2 is a diagram showing voltage waveforms related to main power sources in the block diagram of FIG. 1. FIG. 3 is a circuit diagram related to a power supply circuit according to an embodiment of the present invention. FIG. 4 is a timing chart diagram of the main parts of the circuit diagram of FIG. 3. FIG. 5 is a timing chart of the main parts of the clock stop detection circuit 84. 1... Crystal oscillator 2... Frequency dividing circuit 3... Counter 4... Decoder, drive circuit 5... Display element 6... Control circuit 7... Heavy load circuit 8... Constant Voltage circuit 9...Power supply control circuit 10...Step-down circuit 82...Timer circuit 84...Clock stop detection circuit Applicant: Seiko Epson Corporation -- Shi'ko J- Procedural amendment (voluntary) 21 Title of the invention Electronic devices (236) Seiko Epson Co., Ltd. Representative Director Tsuneya Nakamura 5, Written amendment to procedures subject to amendment 1, amending the name of the invention to "electronic device." 2. Amend the claims as shown in the attached sheet. 3. In the 12th and 14th lines of page 2 of the specification cylinder, the words ``electronic watch'' should be corrected to ``electronic device.'' 4. Delete the text from page 2, line 15, ``The present invention'' to page 3, line 6, ``It is in.'' 5. On page 3, line 7 of the specification tube, the phrase "for watches" should be corrected to "for electronic devices such as electronic watches." 6. On page 4 of the specification, from line 11, ``the present invention'' to line 16, ``described,'' shall be amended as follows. "In view of the above, the object of the present invention is to provide an electronic watch or other electronic watch that uses a battery with relatively high battery voltage and high internal resistance, and uses a step-down circuit to step down the battery voltage and supply it to an electronic circuit including an oscillation circuit. In the device, by forming a stable constant voltage when a battery is inserted and supplying it to the electronic circuit including the oscillation circuit, the oscillation circuit can reliably start oscillating without external operation, and the oscillation can be rapidly stabilized. Hereinafter, the present invention will be described in detail based on an example of an electronic watch, which is a typical electronic device.''7, Specification, page 16, 6
From the line "same circuit" to the seventh line "becomes.""The same circuit is 1024) (z clock signal is input, the capacitor 39 is discharged via the inverter 74.75 and the resistor 40, and the output Sh This sh becomes a 1024 Hz delayed output St whose waveform is shaped by the inverter 76. The EX-OR gate 73 inputs T1-F'E and SN and outputs Sj. -FET
28 forms a charging/discharging circuit, and the output Sj is connected to a MOS
-FET 28 receives and discharges capacitor 38. Therefore, when the clock signal is stopped, Sk is charged and becomes Low.
becomes. As a result, the output Sl of the clock stop detection circuit is normally low.
ow, becomes High when the clock stops. ” he corrected. 8. From page 18, line 10 of the specification, “This invention” to page 19, 1
Correct the lines up to "desu" as follows. "According to the present invention, the oscillation circuit can start automatically at 611X when the battery is inserted, and high step-down efficiency can be obtained under normal conditions, so the electronic device has a long battery life and has a highly stable electronic circuit when the battery is inserted. Although the embodiments have been described using a lithium battery, the present invention is not limited to this, and the present invention can also be applied to electronic devices using other batteries having a relatively high voltage. ” Scope of Claims

Claims (2)

[Claims] (1) Time standard source, electronic circuits such as frequency dividing circuits, display means,
Heavy load circuits such as power batteries, lamps, alarms, etc. through which relatively large currents flow, clock stop detection circuits using the frequency division output of the frequency divider circuit as the clock input, and [a] series/parallel multiple capacitors using MOS/TR. A capacitor step-down circuit that steps down the voltage of the power supply battery by switching. [A] A constant voltage circuit composed of a MOS/TR that steps down the voltage of the power supply battery to a constant voltage lower than the voltage of the power supply battery. [C] When the heavy load circuit is not operating, the capacitor step-down circuit is operated to output the capacitor step-down circuit output voltage, and when the heavy load circuit is operating, the clock stop detection circuit determines that the clock has stopped. An electronic timepiece comprising at least a power supply circuit comprising a power supply control circuit that operates the constant voltage circuit to output a constant voltage circuit output voltage. (2) When the clock stop detection circuit determines that the clock has stopped, the voltage dividing ratio of the resistor for setting the output voltage of the constant voltage circuit is changed to make the output voltage of the constant voltage circuit higher than when the load is heavy. An electronic timepiece according to claim 1.