JPS5870630A - Oscillation stop detecting circuit - Google Patents

Abstract

PURPOSE:To realize the stop of oscillation and automatic restoration, by charging a capacitor through the use of an oscillation output and monitoring a terminal voltage of this capacitor. CONSTITUTION:Signals having phases not overlapped with each other are applied to transistors (TRs) 26, 27 connected in series. When the TR26 turns on, a capacitor 28 is charged an the charge is shared for capacitors 28 and 29 when the TR27 turns on. The capacitors 28, 29 are both charged up to -3V. Then, a TR31 also turns on and the output of an inverter 34 goes to ''L''. When oscillation is stopped, since one of the TRs 26, 27 turns off, the charges 28, 29 are discharged and the inverter 34 goes to ''H'' level. A power supply voltage converting circuit 6 supplies -1.5V to the oscillating circuit when the output of the inverter 34 is ''L'' level and supplies -3V at ''H'' level.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an oscillation stop detection circuit that can detect the stop of oscillation output.

Conventionally, digital watch LSIs operate by using a silver oxide battery (potential difference 1.55V) as a voltage source and using a crystal resonator to obtain an oscillation output at a reference frequency. The output signal was obtained by dividing the frequency and using a booster circuit using a capacitor (capacitance).

However, in order to reduce the current of LSI specifications for digital watches, a lithium battery (potential difference 3.
OV), new problems have arisen. In other words, it is a system in which crystal oscillation is performed at 1.6V, and the potential of the lithium battery is divided to obtain 1.6V using an output signal obtained by dividing the reference frequency obtained by the crystal oscillation and a voltage dividing circuit using a capacitor (capacitance). When configuring an LSI using this method, once the crystal oscillation stops, the voltage divider circuit stops working, making it impossible to obtain a voltage of 1.6V again, resulting in the inconvenience that the crystal oscillation circuit stops working forever. Ta. Therefore, if the crystal oscillation stops for some reason during operation, turn off the power to the crystal oscillation circuit in step 3. Ov to perform crystal oscillation, obtain a potential of 1.5V by the voltage divider circuit, and then change the power supply potential of the crystal oscillation circuit again to 3.5V. It became necessary to change from OV to 1.6V, and a circuit to detect when crystal oscillation had stopped and an oscillation backazop system were required.

As shown in FIG. 1, such a circuit system divides the output signal (a) of the crystal oscillation circuit 1 by a frequency dividing circuit 2,
Using the positive phase (b) and negative phase (C) signals of the frequency divided signal, a capacitor 11
By adding , the negative phase signal is delayed, and when the crystal oscillates, a pulse output is outputted to the output terminal of the exclusive NOR circuit 12 which receives the positive phase signal and the negative phase signal as shown in FIG. 2(d). When the crystal oscillation is stopped, a low-level DC signal (6) is output, and this output terminal is used as an input.
Channel transistor 3, capacitor 14 and load p
An oscillation stop detection circuit was devised in which a detection circuit section using a channel transistor 6 obtains a DC low potential level (g) during oscillation operation and a DC high potential level (f) when oscillation is stopped. That is, the voltage of the crystal oscillator circuit 1 was controlled by the voltage converter circuit 3 which inputs the level-adjusted outputs of the inverter circuits 16 and 17.

However, in this oscillation stop detection circuit, it is necessary to add a large capacity 11 to the inverter circuit 1° in the previous stage in order to obtain a pulse output from the exclusive noise circuit 12 during oscillation operation. The power consumption in the circuit 1o is large, and because of this capacitance 11, the transient response time of the input signal to the exclusive noor circuit 120 is long, and the current consumption in this exclusive noor circuit also becomes large.

Therefore, the present invention focuses on these drawbacks and aims to provide an oscillation stop detection circuit with low power consumption. FIG. 3 is a circuit diagram of an oscillation backup system according to an embodiment of the present invention.

The output terminal of the crystal oscillator circuit 4 is connected to the input terminal of the frequency divider circuit 60, and the intermediate output terminal 18 of the frequency divider circuit 6 is connected to a voltage conversion circuit 19 that converts the low level from -1.5V to -3.OV.
The entire output terminal of the inverter circuit 20 is connected to the input terminal of the inverter circuit 2o, and the output terminal of the inverter circuit 20 is connected to each input terminal of the NOR circuit 21, 22, while the other intermediate output terminal 23 of the frequency dividing circuit 5 is at a low level. -1,5v to -3,
The voltage conversion circuit 24 that converts to OV is connected to the NOR circuit 22.
and the input terminal of the inverter circuit 25, and the output terminal of the inverter circuit 25 is connected to the other input terminal of the NOR circuit 21 described above.

The output terminal of the NOR circuit 21 is connected to the gate electrode of the transistor 26, the output terminal of the NOR circuit 22 is connected to the first flash terminal of the transistor 260 and the gate electrode terminal of the transistor 27, and the drain electrode of each of the transistors 26 and 27 is connected to the output terminal of the NOR circuit 21. A capacitance of 28.29 is connected between the terminal and the board, respectively. The drain electrode terminal of the p-channel transistor 30 for loading is further connected to the drain electrode terminal of the transistor 27, and -3.0V (1) is connected to the gate electrode terminal of the p-channel transistor 3o.
A low level, -ffz-J-)CH'i S 82 level potential is connected, and a VDD level potential (ov) is connected to the source electrode terminal.

Furthermore, the gate electrode terminals of the p-channel transistor 31 and the n-channel transistor 32 are connected to the drain electrode terminal of the transistor 27, and the source electrode terminal of the p-channel transistor 31 is connected to a potential at the level "/DI)," The gate electrode terminal and drain electrode terminal of the n-channel transistor 33 are connected to the source electrode terminal of the n-channel transistor 320, and the source electrode terminal of the transistor (is connected to a potential at the VS52 level), and the switching of the inverter circuit by the transistors 31 and 32 is performed. The level is shifted by the threshold voltage of the transistor 33 toward the negative level side.

The drain electrode terminals of the transistors 31 and 32 are connected to the input terminal of the inverter circuit 240, and the inverter circuit 3
By the current-voltage conversion circuit 6 which inputs the output terminal of 4,
It is configured to control the power supply voltage of the crystal oscillation circuit 4.

Next, the operating principle of this circuit will be explained with reference to FIG.

First, a crystal resonator with a fixed M vibration frequency of 32768112 is used, the output terminal 18 of the frequency dividing circuit 5 is the output terminal of the third stage flip-flop, and the other output terminal 23 is the output terminal of the fourth stage 7 flip-flop. It will be explained as follows. From crystal oscillator circuit 4, 32768II '< (7) Reference signal C
High level is VDD level (OV), low level is vS
8 level (-1.5V) (Fig. 4, 11)], the output terminal 18 has a duty of 5 degrees and the low level is VSS1.
A 4096Hz signal of 4096Hz is obtained, and a 4096H2 signal of low level VSS2 is output to the output terminal of the voltage conversion circuit 19.
On the other hand, the output terminal 23 receives a signal of 2048H2 with a duty of so% and a low level of VSS1, and the output terminal of the voltage conversion circuit 24 receives a signal of 2048H2 with a low level of VSS2.
12 signals [Fig. 4(C)] are obtained.

Therefore, the output terminals of the NOR circuits 2'1 and 22 have a duty ratio of 25 so that the high levels never overlap.
20481-IZ signal [Figure 4(e).

(d)].

When the output terminal of the NOR circuit 21 is at the NO level, the transistor 26 becomes conductive, and the capacitor 28 is charged with the level of the output terminal of the NOR circuit 22, that is, the vSS2 level. Next, when the output terminal of the NOR circuit 22 is at a high level, the transistor 26 becomes non-conductive, the transistor 27 becomes conductive, and the charge is distributed between the capacitor 28 and the capacitor 29.

If the on-resistance of the transistor 30 is very high, that is, several six megaohms, the transistor 26 and the transistor 27 are alternately conductive and non-conductive in the excavation steady state, and the capacitors 28 and 29 are both charged to the VSS2 level ( In Fig. 4 (0° (g)), the potential of the drain electrode terminal of the transistor 27 (dV S becomes 32 level).Therefore, the transistor 31 becomes conductive and the output terminal becomes high level (Fig. 4 (h)). As a result, the output terminal of the inverter circuit 34 has a low level DC potential (i
).

Next, considering when the oscillation operation is stopped, due to the circuit configuration, the output terminals of at least one of the NOR circuits 21 and 22 are at the VSS2 level, and at least one of the transistors 26 and 27 is in a non-conducting state, resulting in a small In both cases, the output terminal point on the side of the capacitor 29 is cut off from the system of the frequency-divided signal from the oscillation.

Therefore, the charge accumulated in the capacitor 29 or both the capacitor 28 and the capacitor 290 is
The state changes to a high level due to the time constant of the capacitance of the sum of i and 29 and the on-resistance of the load transistor 30.Therefore, the output terminal of the inverter circuit 34... Become.

As can be understood from the above explanation, when the crystal oscillation is steady, the output terminal of the inverter circuit 34 is at a low level, and when the crystal oscillation stops tL, the output terminal automatically turns off. Therefore, when the input signal to the power supply voltage conversion circuit 6 is low level, the low level potential of the oscillation circuit 40 is changed to vSS level (
-1,6V), and when the human7°J signal is high level, the low level potential of the oscillation circuit 4 is set to VSS2 level (-3,6V).
If the circuit is designed so that the voltage is 0 V), oscillation can be automatically restored even if the crystal light V stops for some reason.

In addition, in Fig. 3, as can be understood from the above explanation, it is not essential to use n-channel trans/metal transistors for transistors 26 and 27, but instead the transistors are switched alternately. If so, a p-channel transistor may be used, and two or more may be connected in series.

If the time constant due to the on-resistance of the transistor 300 and the capacitor 29 can be made sufficiently larger than the period of the output signal of the NOR circuit 22, the transistor 33 is not necessary, and furthermore, the oscillation circuit is limited to a crystal oscillation circuit. However, in the conventional oscillation stop detection circuit shown in FIG. 1, the inverter circuit 10 is ft)) l (C)
As a result, the inverter circuit is forced to consume several microamperes or more of current during transient response. Furthermore, since the human input signal of the exclusive NOR circuit 12 also has a long transient response time, current consumption of several microamperes or more is forced. The output waveform of the exclusive noise circuit 12, especially the blank period, is based on this transient response time, so the operation can be determined with certainty.
In addition, it is necessary to finely adjust the μ source potential of the equal knob NOR circuit 12, the output potential of the inverter circuit 1o, and the timing, which results in very little design margin. It became necessary to control process parameters such as conductance with high precision, leading to a decrease in manufacturing yield.

However, in the present invention, the oscillation stop detection circuit is not based on the transient response time of the output signal from the frequency dividing circuit, but is configured entirely with digital logic except for the output section of the load transistor 3o. The total current consumption of the oscillation stop detection circuit can be kept to a few nanoamperes, and this circuit section does not require particularly precise process parameters, resulting in a dramatic increase in yield compared to conventional products. be able to.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an oscillation backup system including a conventional oscillation stop detection circuit, Fig. 2 (a) to (g) are signal waveform diagrams of various parts of Fig. It is a waveform diagram of each part. 4... Oscillation circuit, 5... Frequency dividing circuit, 6
...Power supply voltage conversion circuit, 30.31...
・p channel transistor, 26, 27, 32.33・
...N-channel transistor, 28.29...
...Capacitor (capacity t4i), 20.25.34...
...Inverter circuit, 21.22...NOR circuit. Name of agent Patent attorney Toshi Nakao Haga 1 person 13
Figure 4 (a) JlflfllllfL-1
------1flllf-20'

Claims (1)

[Claims] At least two switching transistors each receiving an oscillation output or a frequency-divided signal from the same output are connected in series, and each of these transistors is given the above-mentioned input signal with a different phase, so that at least one of The oscillation stop is characterized in that the transistor is kept non-conductive, and a capacitor is attached to the output terminal side of each of the switching transistors, and the stop of the oscillation output is detected by reversing the potential level of the capacitor end. detection circuit.