JPH0792506B2 - Electronic clock - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a configuration of a power supply unit in an electronic timepiece such as a quartz timepiece which uses electric energy as an energy source. In particular, the present invention relates to improvement of a power supply unit of an electronic timepiece having a power supply whose discharge characteristic is not flat but whose voltage changes as discharge progresses.

[Prior art]

Conventionally, an electronic timepiece such as a quartz timepiece that uses electric energy as an energy source has used a power source having a flat discharge characteristic such as a silver battery in its power source section. As a result, the energy of the power source was fully utilized. However, silver batteries are expensive, and the battery itself has a long life.

As a solution to these problems, alkaline manganese batteries have come to be used in recent years in terms of price, and regarding the life of the battery itself, a watch using a solar battery as a power source and a high-capacity capacitor as a secondary battery has also been proposed. .

However, the alkaline manganese battery does not have a flat discharge characteristic and has a large amount of energy even after the operation of the timepiece is stopped, so that it cannot be said that the characteristics of the battery are sufficiently utilized. Further, in the case of using a high-capacity capacitor as a secondary battery, naturally, the discharge time of the capacitor determines the connection time until the clock stops, which is a big problem for practical use.

〔Purpose〕

An object of the present invention is to provide a timepiece having a timepiece circuit that can drive the timepiece immediately after the oscillation circuit is stopped.

〔Overview〕

The electronic timepiece of the present invention is an electronic timepiece that includes a power generation unit that generates power based on energy applied from the outside, wherein a first capacitor charged by the power generation unit via a rectification unit and a power supply for a timepiece body are provided. A second capacitor having a smaller capacity than the first capacitor, an oscillation circuit connected in parallel to the first capacitor and outputting its operation signal to a booster in a subsequent stage, and whether the oscillation circuit is oscillating. An oscillation detection circuit for detecting whether the oscillation circuit stops oscillation, and a connection from the power generation means to the first capacitor when the oscillation detection circuit detects that oscillation of the oscillation circuit has stopped is connected to the oscillation circuit from the power generation means. Switching means, detecting means for detecting the terminal voltage of the first or second capacitor, and a plurality of capacitors, and the first means based on the detection voltage of the detecting means. And a step-up means for stepwise changing the step-up ratio to the second capacitor by switching the connection of a capacitor and at least two or more capacitors, so that the second capacitor voltage is kept within a certain range by the step-up means. It is characterized by being controlled by.

〔Example〕

The present invention will be described with reference to the drawings according to an embodiment. This embodiment is a timepiece using a solar battery as a power generation mechanism and an electric double layer capacitor which is a high capacity capacitor as a secondary battery.

FIG. 1 is a discharge characteristic of this electric double layer capacitor, and FIG. 2 is a block diagram of an embodiment according to the present invention. FIG. 3 is a circuit diagram of a conventional system. Conventionally, in FIG. 3, when the electric power generated by the solar battery 1 is charged in the electric double layer capacitor 12 and charged to a voltage higher than the rated voltage, the limiter switch 13 is closed and the capacitor 12 is closed.
Stop charging. The timepiece body 14 operates by using the solar battery 11 or the condenser 12 as a power source. The diode 15 is a backflow prevention diode that prevents a current from flowing into the solar battery 11 when the generated voltage of the solar battery 11 becomes equal to or lower than the charging voltage of the capacitor 13.
The discharge characteristics of the capacitor 12 after the solar battery 11 is not exposed to light while the capacitor 12 is fully charged are shown by the solid line VSS ₂ and the broken line V′SS ₁ in FIG.
The vertical axis represents the voltage of the condenser 12, and the horizontal axis represents time. The rated voltage of the capacitor in this embodiment is 1.8V. In addition, the operation stop voltage of the timepiece is 0.9V. At this time, the watch does not work until the solar battery is exposed to light.
It will stop in ₂ hours.

FIG. 2 is a block diagram of an embodiment according to the present invention,
The electric power generated by irradiating the solar battery 1 with light is charged into the electric double layer capacitor 4 through the backflow prevention diode 3. At this time, when the generated voltage (VSS ₁ ) of the solar battery 1 exceeds the rated voltage, the limiter circuit 2 operates and the charging of the capacitor 4 is stopped. For example, the rated voltage is the rated voltage of the capacitor 4, and the limiter circuit is composed of a constant voltage diode. In the figure, when VDD-VSS ₁ exceeds the rated voltage, the power is turned on and the charging current is bypassed, or VDD-VSS There is a switch between ₁ and it is configured to bypass the charging current by detecting the reference voltage. The power charged in the capacitor 4 is optimally boosted by the multi-stage boost charging circuit 5 and charged in the capacitor 6. A detailed description of this operation will be given later. The capacitor 6 serves as a power source for the voltage detection circuit 7 for detecting the voltage VSS ' ₁ of the capacitor 4, the control circuit 8 for causing the boost charging circuit to perform optimum boost charging based on the voltage detection output, and the clock circuit 9. .

Next, the operation of this embodiment will be described in detail with reference to FIG. Here, in FIG. 1, the broken line shows the absolute value of the voltage VSS ′ ₁ of the large capacity capacitor 4, and the solid line shows the absolute value of the voltage VSS ₂ of the capacitor 6. The time when the solar battery 1 is not exposed to light after the capacitor 4 is fully charged will be described. Capacitor 4 voltage | VSS ′ ₁ | is 1.2V
In the above case, the boost charging circuit 5 operates so that the capacitors 4 and 6 have the same voltage (see FIG. 1).
It is an interval from T _{0 to} t ₁ . ). Capacitor 4 voltage | VSS '
_{When 1} | is 1.2V to 0.8V, the boost charging circuit 5 boosts the voltage 1.5 times and charges the capacitor 6. FIG. ₁ is a section from t _{1 to} t ₃ . Therefore, the voltage of capacitor 6 at this time | VSS
₂ | is between 1.8V and 1.2V. Voltage of capacitor 4 | VSS ′ ₁ |
Is 0.8V to 0.6V, the boost charging circuit 5 doubles the voltage and charges the capacitor 6. In FIG. 1, t _{3 to} t ₄
Is the section of. The voltage of capacitor 6 at this time | VSS ₂ |
It will be 1.6V to 1.2V.

When the voltage | VSS ' ₁ | of the capacitor 4 is 0.6 V or less, the boost charging circuit 5 boosts the voltage three times to charge the capacitor 6. It is after t ₄ in FIG.

As described above, according to the present embodiment, the voltage of the capacitor 6 serving as the actual power source of the watch body is boosted by the boost charging means.
By keeping | VSS ₂ | above the operation stop voltage of 0.9 V or more, the operable time of the watch is extended from t ₂ hours to t ₅ hours in FIG. Further, in terms of the voltage of the capacitor 4, what was conventionally usable only between 0.9 V and 1.8 V, but according to the present embodiment, it can be used from 0.3 V to 1.8 V, and the energy stored in the capacitor 4 can be used effectively. It is connected.

Next, specific examples of the multi-stage boosting charging circuit 5, the voltage detection circuit 7, and the control circuit 8 in this embodiment will be described.

FIG. 4 shows a basic form of the multi-stage boosting charging circuit 5, and FIG. 5 specifically shows the operation thereof. (A) shows a boosting operation, and (b) shows a charging operation. The capacitors 4 and 6 in FIGS. 4 and 5 are the same as those in FIG. 2, and the capacitors 21 and 22 are auxiliary capacitors for boosting. Also, Tr _{1 to} T in Fig. 4
r ₇ is a FET and plays the role of a switch for boosting. In Figure 4, without boosting, VSS ' ₁ and VSS
_{To make 2 the} same potential, turn on Tr ₃ and Tr ₄ , and turn off the others. This state is shown in FIG. 5 (A), which is the operation from t ₀ to t ₁ in FIG. Also, t _{1 to} t ₃
In order to perform 1.5 times boosting charge in the boost time Tr _1, T
r _3, Tr ₆ was ON OFF the other, turning OFF the other ON the charging time _{Tr 2, Tr 4, Tr 5} , Tr 7. Similarly, in order to perform double boost charge at t ₃ to t ₄ , Tr ₁ , Tr ₃ , Tr ₅ , Tr ₇ are turned on during boost and the others are turned off. performs a similar operation, in order to perform further t ₄ ~t ₅ 3:00 boosting the voltage step-up 2
Performs the same operation as when the booster during times boosting charge and OFF the other ON the Tr _2, Tr _4, Tr ₆ during charging. As above, each FET
If the control is performed, the state shown in FIG. FIG. 6 shows an embodiment of the multi-stage boosting charging circuit 5 which is realized by an electronic circuit. In FIG. 6, capacitors 4, 6, 2, 22 and FETs Tr _{1 to} Tr ₇ are the same as those in FIG. However, since current flows in both directions in Tr ₅ , Tr ₆ , and Tr _7, both P-channel FET and N-channel F
Combining ET. Further, φCL is a boost charging clock, which boosts when the signal is at the logic level "L" and charges when it is at "H". Therefore, the circuit repeats boost charging according to the cycle of φCL. AmpN, Amp1.5, Amp2, Amp
Reference numeral 3 is a signal indicating a boosting ratio, and when it is "H", it represents no boosting, 1.5 times boosting, 2 times boosting, and 3 times boosting, and the signal is formed by the control circuit 8. In addition, 61 to 64 are known logic gates, and these gates enable Tr ₁ to Tr ₇
The ON / OFF timing of the FET is created, and the operation described with reference to FIGS. 4 and 5 is performed.

Next, FIG. 7 shows a specific example of the voltage detection circuit 7. SP 'is a sampling signal and the circuit operates when it is "H",
When "L", the circuit state is fixed so that current is not wasted. The inside of the broken line is a known constant voltage circuit, and its output voltage is
It is represented as VREG. R ₁ and R ₂ are resistors, and | VSS ′ ₁
With a maximum voltage of 1.8V Is set to satisfy. r ₁ , r ₂ , r ₃ and R are also resistors, so that | VM | and tap potential become the same when | VSS ′ ₁ | becomes 0.6V, 0.8V and 1.2V, respectively. It is set. One of these three tap potentials is selected by the transmission gate 71 (VREGT) and compared with VM by the comparator 72. The comparator 72 outputs "H" if VM is lower than the selected tap potential,
In the opposite case and when SP 'is "L", it is configured to output "L", and its output comp is sent to the control circuit 8. T _1.5 , T ₂ and T ₃ are signals for selecting the transmission gate, which are formed by the control circuit 8 and turn on the transmission gate when the signal is “H”. With the above configuration, VM
And VREGT are compared, and VSS ' ₁ exists in any of t ₀ to t _{5 in} FIG. _{1 in} the state of the result (comp) and the transmission selection signal (T _1.5 , T ₂ , T ₃ ). It becomes possible to judge whether or not. This determination is performed by the control circuit 8 described later.

FIG. 8 is a specific example of the control circuit 8, and FIG. 9 is its timing chart. The timing chart shows the transition from the 1.5 times boost control state to the 2 times boost control state on the left side of the wavy line, and each signal at the time of transition from the 2 times boost control state to the no boost state on the right side of the wavy line X. Shows the movement of. In FIG. 8, 91 and 94 are CL
D-type flip-flop that latches data at the trailing edge of
92 is a master latch that holds data at “L” of CL, 93
Is a 2-bit binary counter, and others are known gates. Here, the operation of this control circuit will be described along the left side of the timing chart wavy line. First, the state before the sampling pulse SP is "H", the step-up ratio of 1.5 times, trans Mitsu Chillon gate selection signal is T _1.5 is "H", the condition is respectively stored in Masutaratsuchi 92 and binary counter 93 Has been done. Now, at the same time that the sampling pulse SP is output, the Reset signal is output to reset the binary counter 93, and the initial state in which T ₃ becomes “H” is restored. After that, T ₃ , T ₂ , and T _1.5 are sequentially selected by the CP pulse until the comparator output comp becomes “L”. Now the voltage of the large capacity capacitor 4 | VSS ′ ₁ | is 0.6 to 0.8
When is between V (between t ₃ ~t ₄ of FIG. 1), as can be seen from the description of FIG. 7, the VM when T ₂ has decreased to "H"
The potential of VREGT reverses and comp becomes “L”. Therefore, the range of VSS ' ₁ can be determined by this. Because the detection potential of T ₃ is 0.6V and the detection voltage of T ₂ is 0.8V, if the output of the comparator is inverted during this period, | VSS ′ ₁ |
Can be specified to be 0.6V to 0.8V. Also,
When | VSS ′ ₁ | is 1.2V or higher, T _1.5 is “H” and comp
Also remains "H". When comp becomes “L”, the subsequent CP
Since the pulse is prohibited, the state of the transmission gate selection signal is stored in the binary counter 93.
When | VSS ′ ₁ | is 1.2 V or higher, T _1.5 is “H” and comp remains “H”. Therefore, it is possible to determine how many times the voltage should be boosted, depending on the contents of the binary counter and the output of comp when the CP pulse ends. The decision is made by the D-type flip-flop 94 and the master latch.
92 and a few gates, which operate at the fall of SP.

As described above, according to this embodiment, the operable time of the timepiece is extended from t ₂ hours to t ₅ hours in FIG.
Moreover, in terms of the voltage of the capacitor 4, the voltage which can be conventionally used only between 0.9V and 1.8V is changed from 0.3V according to this embodiment.
It is clear that it can use up to 1.8V and effectively uses the energy stored in capacitor 2.

Also, in this embodiment, the booster unit 5 in FIG.
Although there are three types of boosting means, that is, two times, 2.0 times, and 3.0 times, and they are used by switching them according to the voltage signal from the voltage detection unit 12, the present invention is not limited to these three types and two types are used. However, various magnifications can be considered. In this embodiment, the voltage detection detects the voltage of the capacitor 4 (1.8, 1.2, 0.8, 0.6V), but it detects the voltage of the capacitor 6 (1.8V, 1.2V) and the contents of the booster 5 are detected. Of course, a method of comparing and determining the boosting state is possible. This method has a merit that the detection voltage is small. Further, the power generation unit 1 is not limited to the solar battery, and may be anything as long as it can generate power.

Further, in FIG. ₁ , the watch stops when V'SS ₁ is between 0.3 V and 0 V, and the oscillator circuit of the watch body also stops oscillating. When the oscillation is stopped, the boosting clock signal is not generated and the boosting operation is also stopped. When the solar cell 1 and the charging circuit are connected in this state, even if the solar cell is irradiated with light, the current flows only into the charging circuit, and the oscillation circuit cannot immediately oscillate. Since it does not work, it takes a considerable amount of time for the watch to drive. In order to solve such a problem, when the oscillation of the oscillation circuit is stopped, the connection between the solar cell and the charging circuit may be disconnected and the solar cell and the oscillation circuit may be directly connected.

A specific example will be described using the example of FIG. In FIG. 10, 102 indicates a clock circuit. The limiter circuit 2 of FIG. 2 is removed for simplification of description, and the multistage booster circuit 5, the voltage detection circuit 7, and the control circuit 8 are replaced by the booster circuit 11.
9. The logic circuit 118 is simplified. 104 is a rectifying means (backflow prevention diode) for preventing current from flowing back to the solar cell 101.

The power supply control will be described below with reference to FIG. First, the secondary battery 103 (capacitor) is set to a low voltage state (0.3 V or less).

If the oscillation signal 123 of the oscillation circuit 108 does not oscillate, the oscillation stop detection circuit 117 detects the stop, the control signal 113 becomes L, the transmission gate 114 is turned on, and the transmission gates 115, 105 are turned off.

Therefore, the power supply 120 of the oscillator circuit 108 is turned off by the booster circuit 119 by the booster circuit 119 and turned on by the solar cell side power source 122. When light is applied to the solar cell 101, the oscillator circuit 108 and the oscillation stop detection circuit are turned on. A voltage capable of oscillating is supplied to 117 and the logic circuit 118, and oscillation is started. When oscillation starts, the boost clock 124 necessary for boosting is generated, and the boost circuit 119 causes the secondary battery 10
The boosting of 3 is started, and a high voltage is generated in the boosting power supply 121. On the other hand, in the power supply gate, the transmission gate 114 turns off and the transmission gates 115 and 105 turn on due to the start of oscillation.
Therefore, in the power supply system of the clock circuit 102, the solar cell 101 charges the secondary battery 103, and the clock circuit 102 operates by the high voltage boosted by the secondary battery 103. That is, even if the secondary battery has a low voltage, the timepiece operates immediately.

〔effect〕

As described above, in the electronic timepiece including the power generation unit that generates power based on the energy applied from the outside, the first capacitor charged by the power generation unit via the rectification unit, and the power source of the timepiece body A second capacitor having a smaller capacity than the first capacitor, an oscillating circuit connected in parallel to the first capacitor and outputting its operation signal to a booster in a subsequent stage, and whether or not the oscillating circuit is oscillating. An oscillation detection circuit for detecting, and when the oscillation detection circuit detects that the oscillation of the oscillation circuit has stopped, switching the connection from the power generation means to the first capacitor to the connection from the power generation means to the oscillation circuit. Means, detection means for detecting the terminal voltage of the first or second capacitor, and a plurality of capacitors, and the first capacitor based on the detection voltage of the detection means. And a step-up means for stepwise changing the step-up ratio to the second capacitor by switching the connection of a capacitor and at least two or more capacitors so that the voltage of the second capacitor is kept within a certain range by the step-up means. By controlling the connection between the first capacitor and two or more capacitors, the stepwise boosting to the second capacitor is possible, and the energy of the first capacitor is not wasted. Can be.

Further, by detecting the operation of the oscillation circuit by the oscillation detection circuit whether or not the oscillation circuit for operating the boosting means is oscillating, when the oscillation circuit stops, the connection between the power generation means and the first capacitor is cut off, Since the oscillation circuit can be directly connected to the electronic circuit, it is possible to provide an electronic timepiece that can immediately operate the timepiece even when the first capacitor has a low voltage.

[Brief description of drawings]

FIG. 1: Dischargeability of a capacitor and an explanatory diagram of the effect of the present invention. FIG. 2: Block diagram of one embodiment according to the present invention. FIG. 3: Diagram of a conventional example. FIG. 4: Diagram showing a basic form of a multistage booster circuit. 5 (A) to (D): A diagram showing a specific example of the operation of FIG. 4. Incidentally, in FIG. 5 (B) to (D), (A) shows the boosting operation,
(B) shows a charging operation FIG. 6: a diagram showing an embodiment as an electronic circuit FIG. 7: a diagram showing a concrete example of a voltage detection circuit FIG. 8: a diagram showing a concrete example of a control circuit FIG. 9: Timing chart of control circuit Fig. 10: Block diagram showing an application example of the present invention. 1 …… Solar battery 2 …… Limiter circuit 4 …… Capacitor 5 …… Boosting means 9 …… Clock body

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-56-10275 (JP, A) JP-A-55-24656 (JP, A) JP-A-57-46186 (JP, A) JP-A-54- 85767 (JP, A) JP 52-30470 (JP, A) Actually developed 55-38249 (JP, U)

Claims (1)

[Claims] 1. An electronic timepiece having a power generating means for generating power based on energy applied from the outside, which serves as a power source for a timepiece and a first capacitor charged by the power generating means via a rectifying means. A second capacitor having a smaller capacity than the first capacitor, an oscillating circuit that outputs its operation signal to a booster in a subsequent stage connected in parallel to the first capacitor, and whether the oscillating circuit is oscillating. An oscillation detection circuit for detecting, and when the oscillation detection circuit detects that the oscillation of the oscillation circuit has stopped, switching the connection from the power generation means to the first capacitor to the connection from the power generation means to the oscillation circuit. Means, detection means for detecting the terminal voltage of the first or second capacitor, and a plurality of capacitors, and the first capacitor based on the detection voltage of the detection means. And a step-up means for stepwise changing the step-up ratio to the second capacitor by switching the connection of at least two capacitors, so that the voltage of the second capacitor falls within a certain range by the step-up means. An electronic timepiece characterized by being controlled by.