GB2158274A

GB2158274A - Electronic timepiece

Info

Publication number: GB2158274A
Application number: GB08507066A
Authority: GB
Inventors: Masahito Yoshino
Original assignee: Suwa Seikosha KK
Current assignee: Suwa Seikosha KK
Priority date: 1984-03-29
Filing date: 1985-03-19
Publication date: 1985-11-06
Also published as: JP2715893B2; JPS61124887A; JPH0792506B2; GB8507066D0; GB2158274B; JPH0772271A

Abstract

An electronic timepiece comprises a first power source (1), e.g. a solar battery, and a second power source (4), e.g. a capacitor, connected to be charged by the first power source. A timepiece movement circuit (9) is arranged to be driven by the second power source. A detector circuit (7) detects the voltage level at a given point. A booster and charger circuit (5) increases the voltage level of the second power source in accordance with the voltage detected by the detector circuit. The booster and charger circuit is located between the second power source and the timepiece movement circuit so that the voltage level applied to the timepiece movement circuit is, in operation, greater than the first predetermined voltage level when the voltage level of the second power source is less than a second predetermined voltage level. <IMAGE>

Description

SPECIFICATION Electronic timepiece This invention relates to electronic timepieces, for example, quartz crystal electronic timepieces.

Conventionally, an electronic timepiece, e.g. a quartz crystal electronic timepiece, has a power source, such as a silver battery, which has a flat discharge characteristic. However, silver batteries are expensive and have a limited life.

One solution to these problems is a power source consisting of an alkali-manganese battery, which is less expensive than a silver battery, in combination with a solar battery and a high capacitance capacitor as a secondary battery. This overcomes the problem of limited battery life.

However, this solution has the disadvantage that the discharge characteristic of an alkalimanganese battery is not flat and, even after the electronic time-piece has ceased operating a significant quantity of energy remains stored in the battery. Consequently, the energy storable in the alkali-manganese battery is not fully utilised.

Further, the use of a high capacitance capacitor as the secondary battery means that the duration of operation until the electronic timepiece ceases operating is limited by the discharge characteristic of the capacitor. Thus the use of a high capacitance capacitor as a secondary battery is not suitable in practice.

Although the present invention is primarily directed to any novel integer or step, or combination of integers or steps, herein disclosed and/or as shown in the accompanying drawings, nevertheless, according to one particular aspect of the present invention to which, however, the invention is in no way restricted, there is provided an electronic timepiece comprising: a first power source; a second power source connected to be charged by the first power source; a timepiece movement circuit arranged to be driven by the second power source; detector means for deecting the voltage level at a given point, and transforming means for increasing the voltage level of the second power source in accordance with the voltage level detected by the detector means, the transforming means being located between the second power source and the timepiece movement circuit so that the voltage level applied to the timepiece movement circuit is, in operation, greater than a first predetermined voltage level when the voltage level of the second power source is less than the second predetermined voltage level.

The detector means ,may be connected to detect the voltage level of the second power source.

An auxiliary capacitor may be connected in parallel with the timepiece movement circuit.

Alternatively, the detector means may be connected to detect the voltage level on the auxiliary capacitor.

In one embodiment the timepiece movement circuit includes an oscillator circuit, means being provided to disconnect the transforming means from the first power source when the oscillator circuit ceases oscillating, so that the first power source drives the oscillator circuit directly.

The first power source may be a solar battery and the second power source may be a capacitor.

The invention is illustrated, merely by way of example, in the accompanying drawings, in which: Figure 1 shows graphically the discharge characteristic of a capacitor; Figure 2 is a block diagram of one embodiment of an electronic timepiece according to the present invention; Figure 3 is a block diagram of a conventional electronic timepiece; Figure 4 shows the basic structure of a booster and charger circuit of the electronic timepiece of Fig. 2; Figures 5(A) to 5(D) are illustrations for explaining the operation of the booster and charger circuit of Fig. 4; Figure 6 is a circuit diagram of another form of booster and charger circuit of an electronic timepiece according to the present invention; Figure 7 is a circuit diagram of a voltage detector circuit of the electronic timepiece of Fig. 2;; Figure 8 is a circuit diagram of a control circuit of the electronic timepiece of Fig. 2; Figure 9 is a timing chart illustrating the operation of the control circuit of Fig. 8; and Figure 10 is a block diagram of another embodiment of an electronic timepiece according to the present invention.

In a conventional electronic timepiece, as shown in Fig. 3, electric power generated by a solar battery 11 is stored in an electric double layer capacitor 1 2 until the voltage level of the capacitor 1 2 exceeds its rated voltage, when a limiter switch 1 3 is closed to prevent further charging of the capacitor 1 2.

A temperature movement circuit 14 is driven by either the solar battery 11 or the capacitor 1 2. A diode 1 5 acts as a reverse-current limiter to prevent current from flowing into the solar battery 11 when the voltage level generated by the solar battery 11 is less than the voltage level of the capacitor 1 2.

Reference is now made to Fig. 1 which illustrates the discharge characteristic of the capacitor 1 2. When there is no illumination of the solar battery 11, with the capacitor 1 2 fully charged, its discharge characteristic is as shown by the broken line. In Fig. 1, the ordinate and the abscissa are the voltage level of the capacitor 12 and time, respectively. In this embodiment, the rated voltage of the capacitor is 1 .8V and the timepiece movement circuit ceases to operation when the drive voltage supplied thereto falls beiow O.9V. Accordingly, the timepiece movement circuit ceases to operate at time t2 when there is no illumination of the solar battery.

Fig. 2 is a block diagram of one embodiment of an electronic timepiece according to the present invention. The electric power produced by illumination of a solar battery 1 charges an electric double layer capacitor 4 through a reverse-current preventing diode 3. When the generated voltage level (VSS1) of the solar battery becomes higher than the rated voltage of the capacitor 4, a limiter circuit 2 is closed to prevent further charging of the capacitor 4.The limiter circuit 2 consists of reference diodes (not shown) and either becomes conductive so that the charging current by-passes the capacitor 4 when the generated voltage level (i.e. the difference between VDD and VSS1) becomes higher than the rated voltage of the capacitor 4 or acts as a switch between VDD and VSS1 so that, when operated, in response to the detection of a reference voltage the charging current by-passes the capacitor. The voltage level V'SS1 on the capacitor 4 is boosted by a multiple booster and charger circuit 5 which charges a capacitor 6.

The capacitor 6 serves as a power source of a voltage detector circuit 7 for detecting the voltage level V'SS1 of the capacitor 4. A control circuit 8 enables the booster and charger circuit 5 to perform proper boosting and charging on the basis of the output voltage of the detector circuit 7 and to provide a drive voltage to a timepiece movement circuit 9.

The operation of the electronic timepiece of Fig. 3 will be explained in detail with reference to Fig. 1. In Fig. 1, the broken line and the solid line show the absolute values of the voltage level V'SS1 of the capacitor 4 and the voltage level VSS2 of the capacitor 6, respectively.

With no illumination of the solar battery and with the capacitor 4 fully charged, when the voltage level V'SS1 of the capacitor 4 is 1.2V or higher, the booster and charger circuit 5 operates to make the voltage levels on the capacitors 4, 6 the same. When the voltage level V'SS1 on the capacitor 4 is between 1.2V and 1.8V, that is, during the period t, to t3 in Fig. 1, the booster and charger circuit 5 boosts the voltage level V'SS1 by a factor of 1.5 and charges the capacitor 6. Accordingly, the voltage level VSS2 on the capacitor 6 is between 1.8V and 1.2V. When the voltage level V'SS1 on the capacitor 4 is between 0.8V and 0.6V, that is, in the period t3 to t4 in Fig. 1, the booster and charger circuit 5 boosts the voltage level by a factor of 2 and charges the capacitor 6.Accordingly the voltage level VSS2 on the capacitor 6 is between 1.6V and 1.2V. When the voltage level V'SS1 on the capacitor 4 is less than 0.6V, that is in the period between t4 and t5 in Figure 1, the booster and charger circuit 5 boosts the voltage by a factor of 3 and charges the capacitor 6.

The booster and charger circuit 5 ensures that the voltage less VSS2 of the capacitor 6, which voltage level powers the timepiece movement circuit 9, is kept above O.9V below which the timepiece movement circuit ceases to operate. Consequently, timepiece movement circuit will continue to operate until time t5 whereas the timepiece movement circuit of the conventional electronic timepiece of Fig. 3 ceases to operate at time t2.

In the conventional electronic timepiece of Fig. 3, the timepiece voltage circuit 14 will only operate if the voltage on the capacitor 1 2 is between O.9V and 1 .8V, whereas in the present invention the timepiece movement circuit will operate if the voltage on the capacitor 4 is between 0.3V and 1.8V and thus the energy stored in the capacitor 4 is fully utilised.

Fig. 4 is a circuit diagram of the booster and charger circuit 5 and Fig. 5 illustrates the operation thereof. The booster and charger circuit 5 comprises field effect transistors (FETs) Tr1 to Tr7 for performing a switching operation, and auxiliary capacitors 21, 22. In order to smoothe the voltage levels V'SS1 and VSS2, when boosting is not performed, the FETs Tr3, Tr4, are turned ON and the FETs Tr1, Tr2, Trs, Tr6, Tr7 are turned OFF. If the FETs Tr1, Tr5 are ON this has little effect as the capacitance of the capacitors 21, 22 is so small that it can be neglected.

The condition of the booster and charge circuit is as represented in Fig. 5(A) and corresponds to the operation during the period to to t, in Fig. 1.

During the period t, to t3, in order to boost the voltage level by a factor of 1.5, the FETs Tr1, Tr3, Tr6 are turned ON with the remaining FETs OFF during voltage boosting and the FETs Tr4, Tr5, Tr7 are ON with the remaining FETs OFF at the time of charging. Similarly, during the period t3 to t4 for boosting by a factor of 2 and charging, the FETs Tr1, Tr3, Tr5, Tr7 are turned ON with the remaining FETs OFF at the time of boosting and the performance of the FETs at the time of charging is the same as that for boosting by a factor of 1.5 and charging. Further, during the period t4 to t5, for boosting by a factor of 3 and charging, the performance of the FETs at the time of boosting is the same as that for boosting by a factor of 2 and charging and the FETs Tr2, Tr4, Tr6 are turned ON with the remaining FETs OFF at the time of charging.

The above-mentioned condition of the FETs for boosting by factors of 1.5, 2 and 3 and charging are illustrated in Figs. 5(B), 5(C) and 5(D), respectively: (a) and (b) indicating boosting operation and charging operation, respectively.

Reference is now made to Fig. 6 which is an illustration of an electronic circuit of another form of booster and charger circuit 5 for an electronic timepiece according to the present invention. In Fig. 6, capacitors, 4, 6, 21, 22 and FETs Tr, to Tr7 correspond to those in Fig. 4, respectively. However, since current flows bi-directionally in FETs Tr5, Tr6, Tr7, these consist of a combination of P-channel FETs and N-channel FETs.

A boosting and charging clock signal CL effects boosting when the logic level thereof is low (L) level and charging when it is high (H) level. Accordingly, the booster and charger circuit of Fig. 6 repeats boosting and charging operations in accordance with the cycle of the clock signal CL. Signals Amp N, Amp 1.5, Amp 2, Amp 3 are signals indicating boosting by factors of 0, 1.5, 2 and 3, respectively, when the logic level of the respective signal is H level. These signals Amp N, Amp 2, Amp 3 are formed by the control circuit (Fig. 2). Logic gate gates 61 to 64 control the ON and OFF states of the FETs Tr, to Tr, to achieve the operation as described with reference to Figs. 4 and 5.

Fig. 7 is an example of the voltage detector circuit 7 in Fig. 2. In response to a sampling signal SP' of H level the voltage detector circuit is actuated. When the sampling signal SP' is L level the voltage detector circuit is locked so that no current flows therethrough. In Fig. 7, the portion enclosed by a broken line is a known reference voltage circuit having an output voltage level VREG. Resistors R1, R2 are designed so that the voltage level VREG with a maximum voltage level 1.8 V of IV'SS1I satisfies the equation: R1 R1 IVREGI = IVMI = -------- IV'SS1 | I = > c x 1.8 R1 + R2 R1 + R2 Resistors r1, r2, r3 are designed so that the tap voltage level is equal to the voltage level VM when IV'SS1 | is 0.6V, 0.8V, 1 .2V, respectively.Among these three tap voltage levels, one voltage level (VREGT) is selected by one of a plurality of transmission gates 71 and the selected tap voltage level VREGT is compared with the voltage level VM by a comparator 72. The comparator 72 provides an output Comp of H level, when the voltage level VM is lower than the selected tap voltage level VREGT and L level when the voltage level VM is higher than the selected tap voltage level VREGT and when the sampling signal SP' is L level. The output Comp is then fed to the control circuit 8 in Fig. 2.

Transmission gate selecting signals T1.5, T2, T3 selecting an appropriate one of the transmission gates 71 are formed by the control circuit 8. In response to one of the transmission gate selecting signals T1.5, T2, T3, being H level the corresponding transmission gate is turned ON.

The voltage detector circuit 7 produces the output Comp from the comparison of the voltage level VM and the selected tap voltage level VREGT and the state of the transmission gate selecting signals T1.5, T2, T3 so that the control circuit 8 determines to which period to to t5 in Fig. 1 the voltage level V'SSi belongs.

Fig. 8 is a circuit diagram of the control circuit 8 and Fig. 9 is a timing chart illustrating the operation thereof. The left half and the right half of Fig. 9 show the signals for transition from a controlling state for boosting by a factor of 1. 5 to a controlling state for boosting by a factor of 2 and for transition from a controlling state for boosting by a factor of 2 to a controlling state where there is no boosting, respectively.

In Fig. 8 D-type flip-flop circuits 91, 94 latch data in response to the rise of the clock signal CL. A master latch 92 holds data in response to the L level of the clock signal CL. The control circuit also has a 2-bit binary counter 93, and the remaining elements are various gates shown by standard symbols.

First, the operation of the control circuit will be described with reference to the left half of the timing chart of Fig. 9. Before a sampling signal SP becomes H level, boosting is by a factor of 1.5 and the transmission gate selecting signal T1.5 is H level. This condition is stored in the master latch 92 and the binary counter 93, respectively. When the sampling signal SP is produced, a reset signal is provided simultaneously, whereby the condition returns to the initial state where the transmission gate selecting signal T3 is H level. Then a signal CP causes the transmission gate selecting signals T3, T2, T1.5 to be selected in turn until the output Comp from the comparator 72 in Fig. 7 becomes L level.

When the voltage level |V'SS1 IT'SKI of the capacitor 4 is in the range 0.6V to 0.8V (i.e. in the period t3 to t4 in Fig. 1) as is apparent from the description of Fig. 7, the voltage levels VM, VREGT are reversed when the transmission gate selecting signal T2 is H level and the output Comp becomes L level and thus the range of the voltage level of V'SS1 is detected. Since the detecting voltage of the transmission gate selecting signal T3 is 0.6V and that of the transmission gate selecting signal T2 is 0.8V, if the output of the comparator is reversed between these voltage levels, the voltage level V'SS1 is defined to be in the range from 0.6V to 0.8V.

When |V'SS1 jV1SSi is 1 .2V or higher, the transmission gate selecting signal T1.5 is H level and the output Comp is also H level. After the output Comp becomes L level, the signal CP is inhibited and the state of the transmission gate selecting signal is stored in the binary counter 93.

Accordingly, depending on the content of the binary counter 93 after the signal CP is inhibited and the state of the output Comp, the appropriate boosting is determined by the Dtype flip-flop 94, the master latch 92, etc., which operate in response to the fall of the sampling signal SP.

In the illustrated embodiment of the present invention, the booster and charger circuit boosts by factors of 1.5, 2 and 3 and an appropriate factor is selected in accordance with the voltage signal from the voltage detector circuit 7. However, the present invention is not limited to such arrangements and the booster and charger circuit can be arranged to boost by one or more factors.

Moreover, though the voltage of the capacitor 4 is detected in the illustrated embodiment of the present invntion, there is the possibility of detecting the voltage of the capacitor 6 and comparing the detected voltage with the content of the booster and charger circuit 5, to determine the boosting amplification factor. This arrangement has the advantage that the voltage detection is realised with a relatively small voltage.

Furthermore, the electronic timepiece can have any form of electronic energy generating device in place of the solar battery 1. Moreover, the solar battery 1 and the limiter circuit 2 can be combined.

Referring again to Fig. 1, when the voltage level V'SS1 is between 0.3V and OV, the timepiece movement circuit ceases to operate and an oscillator circuit thereof ceases oscillation.

When oscillation ceases, the clock signal CL is not produced and so the booster and charger circuit is not actuated. In such a condition, if the solar battery is connected with the booster and charger circuit, electric current generated by the solar battery 1 in response to illumination thereof only flows to a charger portion of the booster and charger circuit. Consequently, the oscillator circuit cannot begin oscillation immediately and a booster portion of the booster and charger circuit is not actuated. Consequently, it takes a considerable time to start operation of the timepiece movement circuit. In order to eliminate this disadvantage, the electronic timepiece is designed so that when the oscillator circuit ceases oscillating, the solar battery is directly connected to the oscillator circuit, breaking the connection between the solar battery and the booster and charger circuit.This is illustrated by the embodiment of the electronic timepiece according to the present invention shown in Fig. 1 0. In Fig. 10, the portion enclosed by the broken line 102 is a timepiece movement driver circuit, the limiter circuit in Fig. 2 being omitted and the booster and charger circuit 5, the voltage detector circuit 7, and the control circuit 8 in Fig. 2 being replaced by a booster circuit 11 9 and a logic circuit 118, respectively, for simplicity of explanation.

Given that a secondary battery or capacitor 103 is in a low voltage state, that is, 0.3V or less and an oscillator circuit 108 does not deliver an oscillation signal 123, an oscillation stop detector circuit 117 stops detection and outputs a control signal 113 of L level which turns a transmission gate 114 ON and transmission gates it 5, 105 OFF.

Accordingly, a power supply line 1 20 for the oscillator circuit 108 is disconnected from a booster power supply line 121 from the booster circuit 119 but is connected to a power supply line 1 22 from a solar battery 1 01.

When the solar battery 101 is illuminated a voltage sufficient to actuate the oscillator circuit 108, the oscillation stop detector circuit 117 and the logic circuit 118 is applied thereto, starting the oscillation. When oscillation starts, a clock signal 1 24 is generated and the booster circuit 119 boosts the secondary battery 103 to a relatively high voltage level.

As oscillation of the oscillator circuit 118 starts, the transmission gate 114 turns OFF and the transmission gates it 5, 105 turn ON. Accordingly, the timepiece movement driver circuit 102 is driven by the high voltage level of the secondary battery 103 which is charged by the solar battery 101. Thus even if the voltage in the secondary battery is relatively low, the timepiece immediately starts operation.

The electronic timepieces according to the present invention and described above have power sources whose discharge characteristic fluctuates and have the effect that loss of electric energy is minimised. In other words, the electric energy of the power source is fully utilised.

Accordingly, by using a capacitor as a secondary power source charged by, for example, a solar battery, battery exchange is avoided, and the operating life of the electronic timepiece is considerably increased. Further, in electronic timepieces using batteries such as alkali-manganese batteries or lithium batteries, energy loss is minimised to a marked extent.

Claims

1. An electronic timepiece comprising: a first power source; a second power source connected to be charged by the first power source; a timepiece movement circuit arranged to be driven by the second power source; detector means for detecting the voltage level at a given point; and transforming means for increasing the voltage level of the second power source in accordance with the voltage level detected by the detector means, the transforming means being located between the second power source and the timepiece movement circuit so that the voltage level applied to the timepiece movement circuit is, in operation, greater than a first predetermined voltage level when the voltage level of the second power source is less than the second predetermined voltage level.

2. An electronic timepiece as claimed in claim 1 in which the detector means is connected to detect the voltage level of the second power source.

3. An electronic timepiece as claimed in claim 1 or 2 in which an auxiliary capacitor is connected in parallel with the timepiece movement circuit.

4. An electronic timepiece as claimed in claim 3 when dependent upon claim 1 in which the detector means is connected to detect the voltage level on the auxiliary capacitor.

5. An electronic timepiece as claimed in any preceding claim in which the timepiece movement circuit includes an oscillator circuit, means being provided to disconnect the transforming means from the first power source when the oscillator circuit ceases oscillating, so that the first power source drives the oscillator circuit directly.

6. An electronic timepiece as claimed in any preceding claim in which the first power source is a solar battery and the second power source is a capacitor.

7. An electronic timepiece substantially as herein described with reference to and as shown in Figs. 2 and 4 to 10 of the accompanying drawings.

8. An electronic timepiece comprising: a first power source and a second power source, said second power source containing a smaller electric energy than said first power source and at least said second power source is chargeable, and a means for supplying an electric energy from said first power source to said second power source including a means for making the voltage level of said first power source and that of second power source different.

9. An electronic timepiece comprising: a plurality of power sources consisting of at least a power source A and power source B, the electric energy of said power source B being smaller than that of said power source A, and at least said power source B of said plurality of power sources being chargeable, and a means to supply the electric energy from said power source A to said power source B, said means to supply the electric energy from said power source A to said power source B including a means to make the voltage levels of said power sources A and B different from each other.

10. An electronic timepiece including a first power source having the generating function, a secondary power source charged by said first power source and a circuit for driving a watch movement, said circuit being driven by said secondary power source, comprising: a detector means for detecting the voltage at the predetermined portion of said circuit, and a transformer for varying the voltage according to the output of said detector means, said transformer being located between said secondary power source and said circuit for driving the watch movement.

11. Any novel integer or step or combination of integers or steps, hereinbefore described and/or as shown in the accompanying drawings, irrespective of whether the present claim is within the scope of, or relates to the same or a different invention from that of, the preceding claims.