JPS5827754B2 - electronic clock - Google Patents

Description

[Detailed description of the invention] The present invention relates to a booster circuit for an electronic watch.

In a fully electronic watch with a display such as a liquid crystal display or a light emitting diode, when operating the above electronic watch with a single battery,
Due to display constraints, a voltage at least twice the battery voltage is required, and a booster circuit is required.

Furthermore, when the power is turned on when replacing batteries, etc., the state of the circuit is not determined and there is a possibility that a display other than the normal state may appear, which is not preferable.

Therefore, it is necessary to generate a reset l- signal when the power is turned on to forcibly reset the circuit to a certain state.

One way to generate the above-mentioned Norisetsu Hm is to differentiate the battery power supply signal, but if the electronic clock is dropped, there is a possibility that a signal will be output even if the battery is momentarily separated. , undesirable.

Therefore, the most suitable structure is to differentiate the boosted power supply and generate the reset signal.

The present invention realizes a booster circuit in which a boosted voltage rises quickly and is suitable for generating the above-mentioned reset signal.

Typical booster circuits include one using a transformer, a Jenkel type booster circuit using a capacitor and a diode, and one using a MOS transistor and a capacitor.

Dienkel type booster circuits that use transformers have many parts and have poor boosting efficiency.

Therefore, a booster circuit using an MO8I transistor and a capacitor is most suitable as a booster circuit for electronic watches because it requires fewer external components and has good boosting efficiency.

However, in this booster circuit, the boosted voltage rises slowly, and this also poses a problem when generating a reset signal.

Therefore, in the present invention, between the battery and the boost power supply,
By installing one diode in the direction of reverse bias, we provide a booster circuit for electronic watches that is the simplest booster circuit but has a quick rise time.

The present invention will be described in detail below with reference to the drawings.

Figure 1 shows an example of a booster circuit using MOS transistors and capacitors used in the present invention, and Figure 2 shows A, B,
In the timing chart of the C signal, 1 is a battery, 5 and 11 are capacitors, 3 and 6 degrees 10 are P-channel MOS transistors, and 2 degrees 4.7, 8 and 9 are n-channel MOS transistors.
S transistors 12-16 are inverters constituted by MO8I-transistors.

Here, transistors 6, 8, 9, and 10 are an interface circuit between a low voltage system and a high voltage system, and the booster circuit is comprised of capacitors 5, 11, and transistors 2, 3, 4, and 7.

First, when the signal A becomes bi-level, the MOS transistor 2 becomes ONL, and one end of the capacitor 5 becomes the negative voltage of the battery 1.

At this time, a bi-level signal is applied to the other end of the capacitor 5 by the signal B, the capacitor 5 is charged, and then the signal A becomes low level, MO8I-transistor 2 is turned off, and the capacitor 5 is charged. When one end of capacitor 5 is disconnected from the battery, signal B also becomes low level, so the other end of capacitor 5 becomes the negative potential of battery 1, and battery 1 and capacitor 5 are connected in series, and the voltage is accumulated. Become.

In this state, the MOS transistor 7 is turned ON by the signal C, and the capacitor 11 is charged with the sum of the voltage of the capacitor 5 and the battery 1, and the voltage - twice the battery voltage Vss.
Create VDD.

FIG. 3 is a circuit that models the booster circuit in FIG.
9, a diode 24, an MO8+-rangestaff is constituted by a switch 30, a resistor 21, a diode 25, and an inverter 13 is constituted by a resistor 18.20, diodes 22, 23, and a switch 28, respectively.

First, when the switch 29 is turned on and the switch 28 is connected to the resistor 20 side, the capacitor 6 is charged by the battery 1.

Next, when the switch 29 is turned off, the switch 30 is turned on, and the switch 28 is connected to the resistor 18 side, the capacitor 6
and the battery 1 are connected in series, and the capacitor 11 is charged to twice the voltage as when the batteries are stacked.

Here, the time from when the battery 1 is connected to the circuit shown in FIG. It is determined by the timing of opening and closing of resistors 18 to 21 and the resistance value of capacitor 6.
Due to the capacitance value limit of No. 11, the time constant is at least several hundred μs or more.

On the other hand, when the power is turned on, the diodes 24 and 25 are in the forward direction regardless of the states of the switches 28, 29 and 30.
A loop is created to charge the capacitor 11.

FIG. 4 shows this situation. The switch 32 is a diagrammatic representation of battery insertion.

FIG. 5 shows the forward VI characteristics of the diodes 24 and 25.

FIG. 6 shows the time characteristics of the voltage (-VDD) of the capacitor 11.

-VDD is the voltage drop of the diode from the battery voltage by 2■
Since the capacitor 11 is rapidly charged, the value increases rapidly up to the value obtained by subtracting o.

However, since it depends on the operation of the booster circuit after that, the increase becomes gradual.

FIG. 7 shows a line of circuits that utilize a boosted voltage to create a reset circuit when the power is turned on.The voltage of the capacitor 11 in FIG. 1, that is, the boosted voltage -VDD, is applied to the input terminal 35, The boosted voltage is differentiated by the resistor @31.

This differential signal is input to an inverter constituted by MOS transistors 38 and 39, and an inverting pulse exceeding the threshold voltage of this inverter is output.

This signal is shaped by an inverter consisting of MO8I transistors 40 and 41, and a reset signal is obtained at terminal 42.

Here, the MOS transistors 38 to 41 cannot operate normally unless VDD is higher than the threshold voltage, so the differential signal must be output after the boosted voltage VDD becomes higher than the threshold voltage of the MOS transistors 38 to 41. A reset signal cannot be obtained.

For this purpose, the differential signal must be output for a period sufficiently longer than the time when VDD reaches the threshold voltage.

However, since the capacitance value of the capacitor 36 is made by diffusion, it is on the order of several PF, and the resistor 37 has a limit of several MΩ, so in the end, the time constant can only be taken from a few microseconds to several tens of microseconds and 4 degrees. I can't.

Therefore, VDD must be made equal to or higher than the thresholds of the MO8I transistors 38 to 41 within several microseconds.

In the booster circuit shown in FIG. 1, the time constant for boosting is several hundreds of microseconds or more, and the voltage drop due to the diodes 33 and 34 has a large 2<o> value, so that the conditions cannot be met.

FIG. 8 shows an embodiment according to the present invention, in which a diode 58 is connected in parallel to transistors 2 and 7 of the booster circuit in FIG.
is inserted.

When the battery 1 is connected to the circuit, the diode 58 becomes forward direction as shown in FIG. 9, and the capacitor 11 is charged.
VDD drops.

The voltage drop due to the diode at this time is approximately 1/2 compared to the case shown in FIG.

FIG. 10 shows the forward VI characteristic of the diode 58, and FIG. 11 shows the -VDD time characteristic.

By providing the diode 58 in this manner, if FIG. 7 35 is connected to FIG. 8 - VDD, VDD becomes the 11th
As is clear from the figure, the value quickly increases to the value obtained by subtracting ■9 from VSS, and also from VSS to ■.

It is easy to make the value obtained by subtracting the value larger than the transistor vth in Fig. 7 by increasing the forward current of the diode 58, and setting the time for VDD to be less than -vth to several μsec. I can do it.

As a result, the boost voltage can rise quickly,
Furthermore, a stable reset signal can be obtained using the circuit shown in FIG.

It is clear from FIG. 3 that even if the diode 58 is added, the diode 58 is reverse biased except when the power is turned on, and does not affect the boosting operation.

As described above, according to the present invention, it is possible to provide a booster circuit with fewer external components and high boosting efficiency.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of a booster circuit constituted by MOS transistors and capacitors used in the present invention. 1...Battery, 2-4, 6-10...
MO8I - transistor, 5, 11... capacitor, 12-16... inverter. FIG. 2 is a timing chart of the first round. Figure 3 is a circuit modeled on Figure 1, with 18 to 21.
...Resistance, 22-25...Diode,
28-30...switches. Figure 4 shows a charging circuit using forward current of a diode.
1...Battery, 32...Switch, 24
゜25...Diode, 11...Capacitor. FIG. 5 shows the forward direction VI characteristics of the diode. Figure 6 shows the time characteristics of VDD. FIG. 7 shows a reset signal circuit, with input terminals 35, 36...
... Capacitor, 37 ... Resistor, 38-4
1... MOS transistor. FIG. 8 shows an embodiment of the present invention, and shows diodes 58. Fig. 9 shows a charging circuit using forward current of a diode. 1...Battery, 32...Switch, 2
4゜25.58...Diode, 11...
...It's a capacitor. FIG. 10 shows the forward direction VI characteristics of the diode.

Claims (1)

[Claims] 1 A closed circuit consisting of a power supply battery, a first capacitor, a first switching MOS transistor, and a second switching MOS transistor, and one end of which is connected to the first switching MO8l-transistor and the second switching MOS transistor.
In the step-up circuit for [3], the booster circuit comprises a second capacitor connected to the connection point of the OS transistor and whose other end is alternately connected to the first or second potential of the power supply battery.
A step-up circuit for a watch, characterized in that a diode is provided which is connected in parallel to the series circuit of the switching MOS transistor and the second switching MOS transistor, and forms a charging loop when the power source battery is turned on.