JP3654878B2 - Output circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an improvement of an output circuit in a semiconductor integrated circuit.
[0002]
[Prior art]
FIG. 7 shows a conventional output circuit. In the figure, 1 is a boosted potential generating circuit, 2 is a delay circuit, C101 is a boosting capacitor at node 2, T101 is a charge transfer transistor for transferring charges from node 3 to node 2, and T1 and T2 are high (hereinafter “ Data output transistor, T3 is Low (hereinafter referred to as “L”) data output transistor, T4 is “H” data reset transistor, and T102 is the gate electrode when the gate electrode of the transistor T101 is boosted. Isolation transistors I1, I2, I3, and I4 for electrically disconnecting from the node 1 are inverters. Here, the transistors T1 to T4 and T101, T102 are NMOS enhancement transistors, and the threshold voltages of the transistors are all set to a predetermined value Vt. An “H” data output signal is input from the input A and an “L” data output signal is input from the input B, and data is output at the output C.
[0003]
Next, the operation of the conventional output circuit configured as described above will be described.
[0004]
First, by setting both the inputs A and B to the “H” level, the output transistors T1 to T3 are all turned off, and the output C becomes High-impedance. (At this time, the transistors T4, T101, T102 are in a conducting state, and the “H” data reset transistor T4 keeps the gate electrode (node 2) of the “H” data output transistor T1 at the “L” level. ).
[0005]
Next, operation waveforms when the output C changes from “High-impedance” to an “L” level output will be described with reference to FIG. The input A remains at the “H” level, so that the “H” data output transistors T1 and T2 remain in a non-conductive state, and the transistors T101, T4, and T102 remain in a conductive state. Here, by changing the input B from the “H” level to the “L” level, the “L” data output transistor T3 becomes conductive, and the output C is output at the “L” level.
[0006]
FIG. 9 shows operation waveforms when the output C changes from “High-impedance” to “H” level output. The input B remains at “H” level, and the “L” data output transistor T3 remains non-conductive. By making the input A “L” level, the node 3 becomes “H” level. For this reason, the “H” data output transistor T2 becomes conductive, and the output C becomes “H” level. However, since the “H” data output transistor T2 is an NMOS enhancement transistor, the voltage of the output C rises only to the potential (Vcc−Vt (threshold voltage)). Further, when the node 3 becomes “H” level, the “H” data reset transistor T4 becomes non-conductive, and the charge is transferred from the node 3 to the node 2 through the charge transfer transistor T101. Charging of the capacitor C101 is performed. At this time, since the potential of the gate electrode of the charge transfer transistor T101 also rises due to the bootstrap effect, charges are accumulated in the node 2 until the power supply voltage (Vcc level) is reached.
[0007]
After that, when sufficient charge is stored in the boosting capacitor C101, the signal of the input A is output after a delay from the delay circuit 2 at this time, so that the node 1 becomes “L” level and the charge transfer transistor T101 becomes non-conductive, and the node 2 and the node 3 are disconnected. Immediately after the node 2 is divided, the node 4 side of the capacitor C101 is pulled up to the “H” level by the output of the “H” level of the inverter I4. Therefore, the node 2 is also boosted by the boosting capacitor C101, and the “H” data The voltage of the gate electrode of the output transistor T1 rises to Vcc + α (= (capacitance of the boosting capacitor C101 (C101) / total capacitance of the node 2 (Co)) × Vcc). Therefore, the output C is for “H” data output. The voltage when the transistor T2 is conductive (Vcc−Vt) is pulled up to the power supply voltage (Vcc).
[0008]
[Problems to be solved by the invention]
However, in the conventional output circuit, it may be difficult to raise the output C to the power supply voltage (Vcc).
[0009]
Therefore, as a result of diligent efforts, the present inventors have learned the following. That is, when noise of an arbitrary time width Δt enters the input A during the “H” data output period from the output C (that is, during the period when the input A is “L” level), the operation of FIG. As shown in the waveform, since the “H” data reset transistor T4 becomes conductive only for a time Δt from the time when noise enters, the charge of the node 2 that has been boosted in advance passes through the “H” data reset transistor T4. After the extraction, even if the time Δt passes and the “H” data reset transistor T4 becomes non-conductive, the potential of the node 2 once extracted does not rise, so that the “H” data output transistor T1 Re-output of “H” data becomes difficult. That is, since the voltage of the gate electrode of the “H” data output transistor T1 boosted by the boosted potential generating circuit decreases due to the noise as described above, the output of “H” data is reduced to a low voltage ( Vcc−Vt) level can only be performed.
[0010]
Further, in the conventional output circuit, when the power supply voltage is lowered, the ratio of the threshold voltage Vt to the power supply voltage Vcc increases, so that the operation of generating the boosted potential of the boosted potential generating circuit becomes very difficult. . This will be described in detail below, taking the case where “H” data is output to the output C at the low power supply voltage Vcc as an example. As an example, description will be made using the circuit of FIG. 7 with the power supply voltage Vcc = 1.5V and the threshold voltage Vt = 0.8V.
[0011]
FIG. 10 shows an operation waveform when “H” data is output to the output C. By fixing the input B to the “H” level and changing the input A from the “H” level to the “L” level, the “L” data output transistor T3 is brought into the non-conductive state, and the “H” data output is performed. The transistor T2 becomes conductive, and "H" data is output. Here, the output C rises only to the potential Vcc−Vt = 0.7V because the “H” data output transistor T2 is an NMOS enhancement transistor. The input A is input to the delay circuit 2 via the inverter I3, and at the same time, the charge starts to be transferred to the node 2 through the charge transfer transistor T101. However, at this time, since the gate electrode of the isolation transistor T102 and the node 1 side are both at the power supply voltage (1.5 V), the potential of the gate electrode of the charge transfer transistor T101 decreases by the threshold voltage Vt. Thus, the potential Vcc−Vt = 0.7 V, and the charge transfer transistor T101 remains in a non-conductive state.
[0012]
That is, even when the node 3 becomes “H” level, the charge transfer transistor T101 is in a non-conductive state, so that no charge is transferred to the node 2 side of the boosting capacitor C101, and the potential of the node 2 is As a result, the initial value of 0 V is maintained, and as a result, the “H” data output transistor T1 cannot output the “H” data of the power supply voltage (Vcc).
[0013]
Accordingly, at the time of a low voltage such as the low power supply voltage Vcc = 1.5V, the boost capacitor C101 is not sufficiently charged, so that the gate electrode of the “H” data output transistor T1 cannot be boosted and the power supply voltage (Vcc "H" data cannot be output.
[0014]
The present invention solves the above-described conventional problems. The object of the present invention is to stably operate the boosted potential generation circuit even when operating at a low power supply voltage, and to ensure that the power supply voltage (Vcc) is “H”. “To provide an output circuit capable of outputting data.
[0015]
[Means for Solving the Problems]
In order to solve the above problem, in the present invention, the supply voltage is supplied as it is to the gate electrode of the charge transfer transistor T101 without causing a decrease in the threshold voltage Vt in the isolation transistor T102, thereby ensuring the reliability. Then, the charge transfer transistor T101 is turned on to charge the boost capacitor reliably.
[0016]
Specifically, an output circuit according to a first aspect of the present invention is an output circuit that inputs an external signal and controls the potential level of the output terminal in accordance with the potential level of the external signal, the output terminal, a power source, A high data output transistor disposed between and a boosted potential generating circuit that is activated by the external signal and charges the gate electrode of the high data output transistor to a high voltage equal to or higher than the voltage of the power supply, The boosted potential generating circuit includes a delay circuit that delays an input external signal for a set time, a first inverse logic circuit that generates an inverse logic of an output signal of the delay circuit, the first inverse logic circuit, and a High A capacitor disposed between the gate electrode of the data output transistor and boosting the gate electrode of the high data output transistor; and a second paradox for generating an inverse logic of the external signal A charge transfer transistor disposed between the logic circuit, the second inverse logic circuit, and the gate electrode of the high data output transistor for charging the gate electrode of the high data output transistor; and the delay A separation transistor disposed between the output side of the circuit and the gate electrode of the charge transfer transistor and a boost pulse having a voltage exceeding the power supply voltage are generated for a predetermined period during which the potential level of the external signal changes. A boosting pulse generation circuit, wherein the boosting pulse of the boosting pulse generation circuit is supplied to a gate electrode of the isolation transistor.
[0017]
According to a second aspect of the present invention, in the output circuit according to the first aspect, the boost pulse generation circuit generates a delay circuit that delays an input external signal for a set time and an inverse logic of the output signal of the delay circuit. An inverse logic circuit; a NOR circuit that receives an output signal of the inverse logic circuit and the external signal that is input; a capacitor disposed on an output side of the NOR circuit; and an output terminal in which the capacitor and the power supply are connected in parallel. It is characterized by comprising.
[0018]
According to a third aspect of the present invention, in the output circuit according to the first or second aspect, the charge transfer transistor and the separation transistor of the boosted potential generation circuit have a threshold voltage of the high data output transistor. It has a characteristic lower than the threshold voltage.
[0019]
Further, according to a fourth aspect of the present invention, in the output circuit according to the first, second, or third aspect of the present invention, the over boosting is connected to the gate electrode of the high data output transistor and exceeds the set voltage of the gate electrode. An over-boosting prevention circuit for preventing the above is provided.
[0020]
According to a fifth aspect of the present invention, in the output circuit according to the fourth aspect, the over-boosting prevention circuit is an over-boosting prevention transistor disposed between the power supply and the gate electrode of the high data output transistor. The over-boost prevention transistor has a gate electrode connected to the gate electrode of the high data output transistor, and a threshold voltage equal to or higher than the threshold voltage of the high data output transistor.
[0021]
With the above configuration, in the output circuit according to any one of claims 1 to 5, the boost pulse generation circuit generates a boost pulse during a period in which the potential level of the external signal changes, and the boost pulse is supplied to the separation transistor. . As a result, the power supply voltage Vcc is supplied to the gate electrode of the charge transfer transistor while maintaining the power supply voltage Vcc without causing a voltage drop by the threshold voltage of the isolation transistor. As a result, the charge transfer transistor is surely turned on, and the charge transfer by the charge transfer transistor to the gate electrode of the “H” data output transistor (charging of the boosting capacitor) can be performed smoothly. Therefore, even when operated with a low voltage power supply, the gate electrode of the “H” level output transistor is surely pulled up to a voltage of Vcc + Vt or more, and the “H” data output transistor T1 causes the “H” level of the power supply voltage Vcc level. Level data can be output reliably.
[0022]
In particular, the threshold voltage of the charge transfer transistor and isolation transistor of the boosted potential generating circuit is lower than the threshold voltage of the “H” data output transistor. Charge through the transistor is efficiently charged, and “H” level data of the power supply voltage Vcc level can be reliably output even during operation using a much lower voltage power supply.
[0023]
According to the fourth and fifth aspects of the invention, the over-boosting prevention circuit prevents over-boosting of the gate electrode of the “H” data output transistor.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Before that, an output circuit having strong noise resistance will be described as a technique related to the present invention.
[0025]
(Related technology of the present invention)
FIG. 1 shows an output circuit according to the related art of the present invention. In the figure, 1 is a boosted potential generating circuit, 2 is a delay circuit, C101 is a boosting capacitor at node 2, T101 is a charge transfer transistor, T1 and T2 are "H" data output transistors, and T3 is "L". A data output transistor, T4 is an “H” data reset transistor, T5 is a noise absorbing transistor (noise absorbing circuit), and T102 is electrically disconnected from the node 1 when the gate electrode of the charge transfer transistor T101 is boosted. Isolation transistor. A and B are input terminals for inputting external signals, C is an output terminal, and I1 to I4 are inverters.
[0026]
A high data output signal is taken in from the input A, and a low data output signal is taken in from the input B. When the output C is not output, both the input A and the input B are at the “H” level.
[0027]
The "H" data output transistor T1 is disposed between the power supply Vcc and the output C. The “H” data reset transistor T4 is disposed between the gate electrode of the “H” data output transistor T1 and the ground terminal D, and a high data output signal to the input A is input to the gate electrode. Is done. The noise absorbing transistor T5 is connected in cascade with the “H” data reset transistor T4, and the output signal of the delay circuit 2 of the boosted potential generating circuit 1 is input to the gate electrode thereof.
[0028]
In the boosted potential generating circuit 1, an inverter (first inverse logic circuit) I4 generates an inverse logic of the output signal of the delay circuit 2, and a capacitor C101 is connected to the output side of the inverter I4 and outputs "H" data. Arranged between the gate electrode of the transistor T1. The inverter (second inverse logic circuit) I1 generates the inverse logic of the high data output signal from the input A, and the charge transfer transistor T101 is the gate of the inverter I1 and the “H” data output transistor T1. It arrange | positions between electrodes. Further, the separation transistor T102 is disposed between the output side of the delay circuit 2 and the gate electrode of the charge transfer transistor T101, and the gate electrode is connected to the power source Vcc.
[0029]
Next, FIG. 2 shows an operation waveform when noise having an arbitrary pulse width Δt enters the input A when the output C is outputting the “H” level.
[0030]
First, when the input A is “L” level and the input B is “H” level, the output C is “H” level. When the input A becomes “H” level due to noise, the “H” data reset transistor T4 at the node 2 is turned on, but the noise absorbing transistor T5 is turned on at the input A. This is the time when the set time T (delay time of the delay circuit 2) after the noise has entered has elapsed. That is, if the noise pulse width Δt is smaller than the delay time T of the delay circuit 2, even if the “H” data reset transistor T4 becomes conductive, the charge of the node 2 passes through the “H” data reset transistor T4. It will not be pulled out. That is, with respect to noise that satisfies Δt <T, the present configuration can absorb noise and stably hold the boosted potential of the node 2.
[0031]
Further, since the “H” data reset transistor T4 and the noise absorbing transistor T5 are connected in series between the gate electrode of the “H” data output transistor T1 which is the node 2 and the ground potential, the output It is also possible to prevent the electric field from being concentrated when the “H” level of C is reset (that is, when the potential of the node 2 is lowered).
[0032]
(Embodiment of the present invention)
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0033]
FIG. 3 shows an output circuit according to the embodiment of the present invention. In the figure, 3 is a boost pulse generation circuit, 4 is an over-boost prevention circuit, and I5 to I8 are inverters. The boost pulse generation circuit 3 is a voltage exceeding the voltage of the power supply Vcc for a predetermined period from the time when the high data output signal from the input A starts to change from "H" level to "L" level to a predetermined time T2. Is generated. Both the charge supply transistor T101 and the separation transistor T102 of the potential generating circuit 1 have characteristics that the threshold voltage is lower than the threshold voltage of the “H” data output transistor T1.
[0034]
The over-boosting prevention circuit 4 has an over-boosting prevention transistor T6, which is disposed between the gate electrode of the “H” data output transistor T1 and the power source Vcc, and the gate electrode is The threshold voltage of the "H" data output transistor T1 is connected to the gate electrode of the "H" data output transistor T1, and is equal to or higher than the threshold voltage of the "H" data output transistor T1.
[0035]
3 is the same as that of FIG. 1, the same reference numerals are given to the same parts, and the description thereof is omitted.
[0036]
The configuration of the boost pulse generating circuit 3 is shown in FIG. In the figure, 5 is a delay circuit that delays the signal from the input A by a set time, I9 is an inverter (inverse logic circuit) that generates the inverse logic of the output signal from the delay circuit 5, and 6 is the output of the inverter I9. A NOR circuit that receives the signal and the signal from the input A, C203 is a capacitor connected to the output side of the NOR circuit 6, and 7 is an output terminal. The output terminal 7 is connected to the capacitor C203 and to a power source Vcc via a resistor R. The boost pulse from the output terminal 7 is supplied to the gate electrode of the separation transistor T102 of FIG.
[0037]
The operation waveforms of the boost pulse generation circuit 3 are shown in FIG. In the boost pulse generation circuit 3 of FIG. 4, when the input signal changes from the “H” level to the “L” level, the node 7 becomes “L” after the delay time T2 including the inverter I5 and the delay circuit 5 has elapsed. The level changes from “H” level. Only when the input signal and the node 7 are at the “L” level simultaneously, the node 8 is at the “H” level. Since the output potential E of the output terminal 7 is normally the power supply voltage Vcc, the potential E of the output terminal is Vcc + β at this time. That is, the waveform of the voltage E at the output terminal 7 of the boost pulse generating circuit 3 is Vcc + β only for the set time T2 after the input signal becomes “L” level, and at other times, the power supply voltage Vcc. ing.
[0038]
Next, FIG. 6 shows an operation waveform when the output C changes from “High-impedance” to “H” level in FIG. In the following description, the power supply voltage Vcc is 1.5 V and the threshold voltage Vt is 0.8 V.
[0039]
First, by setting both the input A and the input B to “H” level, the transistors T1 to T3 are turned off, and the output C becomes “High-impedance”.
[0040]
When the input A is changed to the “L” level, the “H” data reset transistor T4 becomes non-conductive, and at the same time, a boost pulse signal generated from the signal of the input A is input to the gate electrode of the separation transistor T102. This state continues until immediately before the node 3 becomes “H” level, and accordingly, the gate electrode of the charge transfer transistor T101 rises to the power supply voltage Vcc. After that, when the node 3 becomes “H” level, the “H” data output transistor T2 becomes conductive and the output C becomes “H” level, but the voltage of the output C is “H” data output. Since the transistor T2 is an NMOS enhancement transistor, it rises only to Vcc-Vt (V) = 0.7V. However, at the same time, when the node 3 becomes “H” level, the charge is transferred from the node 3 to the node 2 through the charge transfer transistor T101, and the charge is stored on the node 2 side of the boosting capacitor C101. The potential of the node 2 rises to the power supply voltage Vcc, and accordingly, the potential of the gate electrode of the charge transfer transistor T101 also rises due to the bootstrap effect. When the charge A is sufficiently accumulated in the boosting capacitor C101, when the signal of the input A is delayed and output by the delay circuit 2, the node 1 becomes "L" level, and the charge transfer transistor T101 becomes non-conductive. Thus, node 2 and node 3 are divided. Immediately after that, the node 4 side of the boosting capacitor C101 becomes “H” level, and the potential of the node 2 side also rises. As a result, the gate voltage of the “H” data output transistor T1 rises to Vcc + Vt or more. The voltage of the output C can be raised from the voltage (Vcc−Vt) when the “H” data output transistor 2 is turned on to the power supply voltage Vcc.
[0041]
As described above, the boosting pulse of the boosting pulse generation circuit 3 is supplied to the gate electrode of the isolation transistor T102, and the potential level of the gate electrode is temporarily boosted, so that the power supply voltage Vcc = 1.5V is obtained. Even when a low voltage power supply is used, the gate electrode of the charge transfer transistor T101 can be sufficiently charged, so that the charging from the node 3 to the boosting capacitor C101 and the boosting operation of the node 2 can be stabilized. Can be done.
[0042]
Further, as the charge transfer transistor T101 and the separation transistor T102, transistors having a threshold voltage lower than the threshold voltage of the “H” data output transistor T1 are used, so that the gate electrode of the charge transfer transistor T101 is used. In addition, it is possible to reduce the influence caused by the drop of the threshold voltage Vt of both the transistors T102 and T101 when the node 2 is charged, and the charging from the node 3 to the node 2 can be performed more efficiently. Therefore, an output circuit that operates reliably even at a lower power supply voltage can be obtained.
[0043]
Further, since the over-boost prevention circuit 3 is inserted into the gate electrode of the “H” data output transistor T1, the voltage of the gate electrode of the “H” data output transistor T1 is a gate that does not cause a drop in the threshold voltage Vt. Although the voltage rises to the voltage (Vcc + VtT6 (threshold value of the transistor T6)), when an excessive boosting is attempted beyond that, the excessive boosting prevention transistor T6 is turned on to prevent the excessive boosting. Therefore, it is possible to prevent an unnecessarily high voltage from being applied to the gate electrode of the “H” data output transistor T1.
[0044]
【The invention's effect】
As described above, according to the output circuit of the first to fifth aspects, the gate electrode of the “H” level output transistor is reliably pulled up to a voltage of Vcc + Vt or more even when operated with a low voltage power supply. Therefore, the “H” level data of the power supply voltage Vcc level can be reliably output from the “H” data output transistor T1.
[0045]
In particular, according to the output circuit of the third aspect of the present invention, each threshold voltage of the boosted potential generating circuit as the charge transfer transistor and the separation transistor is higher than the threshold voltage of the “H” data output transistor. Since the low voltage is used, the charge can be efficiently charged through the charge transfer transistor, and the “H” level data of the power supply voltage Vcc level can be reliably obtained even when operating with a lower voltage power supply. Can output.
[0046]
According to the output circuits of the fourth and fifth aspects of the present invention, since the over-boosting prevention circuit is provided, over-boosting of the gate electrode of the H ″ data output transistor can be prevented.
[Brief description of the drawings]
FIG. 1 is a diagram showing an output circuit according to a related art of the present invention.
FIG. 2 is a diagram showing a noise waveform at a low voltage by the output circuit.
FIG. 3 is a diagram illustrating an output circuit according to the embodiment of the present invention.
FIG. 4 is a diagram showing a boost pulse generation circuit of the output circuit according to the embodiment;
FIG. 5 is a diagram showing operation waveforms of the boost pulse generation circuit according to the same embodiment;
FIG. 6 is a diagram showing an output waveform at the time of High output at the time of low voltage by the output circuit of the same embodiment;
FIG. 7 is a diagram showing a conventional output circuit.
FIG. 8 is a diagram illustrating operation waveforms at the time of Low output by a conventional output circuit.
FIG. 9 is a diagram illustrating operation waveforms at the time of High output by a conventional output circuit.
FIG. 10 is a diagram illustrating an output waveform when a high voltage is output at a low voltage by a conventional output circuit.
FIG. 11 is a diagram showing an operation waveform of a conventional output circuit when noise occurs at a low voltage.
[Explanation of symbols]
C output terminal Vcc power supply T1 "H" data output transistor 1 boost potential generation circuit D ground terminal T4 "H" data reset transistor T5 noise absorbing transistor (noise absorbing circuit)
2 Delay circuit I4 Inverter (first inverse logic circuit)
I1 Inverter (second inverse logic circuit)
C101 capacitor C102 capacitor (capacitance value: C102)
Co node 2 Total capacitance value T101 Charge transfer transistor T102 Separation transistor 3 Boost pulse generation circuit 4 Over-boost prevention circuit T6 Over-boost prevention transistor 5 Delay circuit I9 Inverter (reverse logic circuit)
6 NOR circuit C203 Capacitor 7 Output terminal

Claims (5)

An output circuit that inputs an external signal and controls the potential level of the output terminal according to the potential level of the external signal,
A High data output transistor disposed between the output terminal and a power source;
A boosted potential generating circuit that is activated by the external signal and charges the gate electrode of the High data output transistor to a high voltage equal to or higher than the voltage of the power supply;
The boosted potential generation circuit includes:
A delay circuit that delays an input external signal for a set time;
A first inverse logic circuit for generating an inverse logic of the output signal of the delay circuit;
A capacitor disposed between the first inverse logic circuit and the gate electrode of the High data output transistor, for boosting the gate electrode of the High data output transistor;
A second inverse logic circuit for generating the inverse logic of the external signal;
A charge transfer transistor disposed between the second inverse logic circuit and the gate electrode of the High data output transistor for charging the gate electrode of the High data output transistor;
A separation transistor disposed between the output side of the delay circuit and the gate electrode of the charge transfer transistor;
A boosting pulse generating circuit for generating a boosting pulse of a voltage exceeding the voltage of the power supply during a predetermined period in which the potential level of the external signal changes;
The boosting pulse of the boosting pulse generating circuit is supplied to the gate electrode of the isolation transistor. The boost pulse generator circuit
A delay circuit that delays an input external signal for a set time;
An inverse logic circuit for generating an inverse logic of the output signal of the delay circuit;
A NOR circuit that receives the output signal of the inverse logic circuit and the input external signal; a capacitor disposed on the output side of the NOR circuit;
2. The output circuit according to claim 1, comprising an output terminal in which the capacitor and the power source are connected in parallel. The charge transfer transistor and separation transistor of the boosted potential generation circuit are:
3. The output circuit according to claim 1, wherein the threshold voltage has a characteristic lower than the threshold voltage of the high data output transistor. 4. An over-boosting prevention circuit that is connected to a gate electrode of a high data output transistor and prevents an over-boosting exceeding a set voltage of the gate electrode. Output circuit. The over boost prevention circuit
An over-boosting prevention transistor disposed between the power source and the gate electrode of the high data output transistor,
5. The over boost prevention transistor has a gate electrode connected to a gate electrode of the high data output transistor, and a threshold voltage is equal to or higher than a threshold voltage of the high data output transistor. The output circuit described.

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